Multi-mode control for a DC-to-DC converter

ABSTRACT

An apparatus includes a voltage regulation module that controls output voltage of a bidirectional DC to DC converter to an output voltage reference over an output current range between a positive power reference and a negative power reference. A positive power regulation module controls output power of the converter to the positive power reference over a positive constant power range between the output voltage reference and a positive output current reference. A negative power regulation module controls output power of the converter to the negative power reference over a constant power range between the output voltage reference and a maximum negative power limit, and a constant current module limits output current to a positive output current reference in a range between a minimum output voltage and output power of the converter reaching the positive power reference.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication No. 62/006,734 entitled “DIRECT CURRENT TO DIRECT CURRENTCONVERTER” and filed on Jun. 2, 2014 for Regan Zane, et al., which isincorporated herein by reference. “Modeling and Control of the DualActive Bridge Series Resonant Converter,” Ph.D. dissertation of DanielSeltzer, submitted to the Faculty of the Graduate School of theUniversity of Colorado, Department of Computer, and Energy Engineering,Jul. 18, 2014 is hereinafter incorporated by reference.

FIELD

This invention relates to direct current (“DC”) to DC converters andmore particularly relates to multi-mode control for DC-to-DC converters.

BACKGROUND

As electrical systems increasingly come to dominate modern life, thepower conversion technologies that enable these systems to efficientlyconnect to one another are becoming increasingly important. With theexpanding demand for such technologies in ever diversifying areas, thedemands placed on power converters have increased in kind. For manyyears switching converters have been able to keep up with theseincreasing requirements by adopting ever more complex power convertertopologies and control schemes. One major development in this area isthe class of resonant switching converters, such as the series resonantconverter. These types of converters have allowed higher efficiencypower conversion with faster response times in a variety ofapplications. Their cost lies in the greater difficulty with which theyare modeled (and thus controlled), and is frequently substantial.

SUMMARY

An apparatus for multi-mode control is disclosed. A system and methodalso perform the functions of the apparatus. The apparatus includes avoltage regulation module that controls output voltage of a directcurrent (“DC”) to DC converter to an output voltage reference over anoutput current range between an operating condition where output powerof the converter reaches a positive power reference and output power ofthe converter reaches a negative power reference. The converter includesa bidirectional converter. The apparatus includes, in one embodiment, apositive power regulation module that controls output power of theconverter to the positive power reference over a positive constant powerrange between the output voltage of the converter being at the outputvoltage reference and output current of the converter being at apositive output current reference. The apparatus, in one embodiment,includes a negative power regulation module that controls output powerof the converter to the negative power reference over a constant powerrange between output voltage of the converter being at the outputvoltage reference and a maximum negative power limit of the converter,and a constant current module that limits output current to a positiveoutput current reference in a range between a minimum output voltage andoutput power of the converter reaching the positive power reference.

In one embodiment, the constant current module includes a currentfeedback control loop that limits output current to below the positiveoutput current reference. In another embodiment, the positive powerregulation module, the negative power regulation module, and the voltageregulation module include feedback control loops and the currentfeedback control loop includes an inner feedback control loop and thefeedback control loops of the positive power regulation module, thenegative power regulation module, and the voltage regulation module forman outer feedback loop. In another embodiment, the constant currentfeedback loop further includes compensation implemented using a gainscheduled feedback controller. The gain scheduled feedback controllerincludes one or more output control signals that vary over a pluralityof control regions, where the gain scheduled feedback controllerimplements a different compensation equation for each control region.

In one embodiment, the converter includes one or more phase shiftmodulators controlled by the one or more output control signals, wherethe one or more output control signals control according to a minimumcurrent trajectory (“MCT”) control technique. The MCT substantiallyminimizes circulating current within the converter. In anotherembodiment, the gain scheduled feedback controller maintains theconverter in a zero-voltage switching (“ZVS”) region while minimizingcirculating current by following a trajectory a fixed distance from anMCT. In another embodiment, the constant current module further limitsthe output current to a negative output current reference in a rangebetween a minimum output voltage and output power of the converterreaching the negative power reference.

In one embodiment, the output voltage reference varies with outputcurrent such that the output voltage reference decreases as outputcurrent increases. In another embodiment, the output voltage referencevaries based on the equation:V _(Set)(I _(O))=V _(Set)(0)−I _(OUT) R _(V)

-   -   where:    -   V_(Set)(I_(O)) is the output voltage reference as a function of        output current;    -   V_(Set)(0) is the output voltage reference at zero output        current;    -   R_(V) is a resistance representing a slope of the output voltage        reference; and    -   I_(OUT) is output current of the converter.

In another embodiment, the positive output current reference varies withoutput voltage such that the positive output current reference decreasesas output voltage increases. In a further embodiment, the positiveoutput current reference varies based on the equation:

${I_{Set}\left( V_{OUT} \right)} = {{I_{Set}(0)} - \frac{V_{OUT}}{R_{I}}}$

-   -   where:    -   I_(Set)(V_(OUT)) is the positive output current reference as a        function of output voltage;    -   I_(Set)(0) is the positive output current reference at zero        output voltage;    -   V_(OUT) is the output voltage; and    -   R_(I) is a resistance representing a slope of the positive        output current reference.

In one embodiment, the converter comprises a resonant power converter.In another embodiment, the resonant power converter comprises at leastone stage of a dual active bridge series resonant converter (“DABSRC”).

A system for multi-mode control includes a DC to DC converter, where theconverter is a bidirectional converter, and one or more phase shiftmodulators controlling one or more phase angles within the converter.The system includes a voltage regulation module that controls outputvoltage of the converter to an output voltage reference over an outputcurrent range between an operating condition where output power of theconverter reaches a positive power reference and output power of theconverter reaches a negative power reference. The system, in oneembodiment, includes a positive power regulation module that controlsoutput power of the converter to the positive power reference over apositive constant power range between the output voltage of theconverter being at the output voltage reference and output current ofthe converter being at a positive output current reference, and anegative power regulation module that controls output power of theconverter to the negative power reference over a constant power rangebetween output voltage of the converter being at the output voltagereference and a maximum negative power limit of the converter. Thesystem, in one embodiment, includes a constant current module thatlimits output current to a positive output current reference in a rangebetween a minimum output voltage and output power of the converterreaching the positive power reference.

In one embodiment, the constant current module includes a currentfeedback control loop that limits output current to below the positiveoutput current reference. In another embodiment, the constant currentfeedback loop also includes compensation implemented using a gainscheduled feedback controller, where the gain scheduled feedbackcontroller includes one or more output control signals that vary over aplurality of control regions, and the gain scheduled feedback controllerimplements a different compensation equation for each control region. Inanother embodiment, the one or more output control signals controlaccording to a MCT control technique. The MCT substantially minimizingcirculating current within the converter, where the gain scheduledfeedback controller maintains the converter in a ZVS region whileminimizing circulating current by following a trajectory a fixeddistance from an MCT.

A method for multi-mode control includes controlling output voltage of aDC to DC converter to an output voltage reference over an output currentrange between an operating condition where output power of the converterreaches a positive power reference and output power of the converterreaches a negative power reference. The converter is a bidirectionalconverter. The method, in one embodiment, includes controlling outputpower of the converter to the positive power reference over a positiveconstant power range between the output voltage of the converter beingat the output voltage reference and output current of the converterbeing at a positive output current reference and controlling outputpower of the converter to the negative power reference over a constantpower range between output voltage of the converter being at the outputvoltage reference and a maximum negative power limit of the converter.The method includes, in one embodiment, limiting output current to apositive output current reference in a range between a minimum outputvoltage and output power of the converter reaching the positive powerreference.

In one embodiment, limiting output current to a positive output currentreference includes using a current feedback control loop that limitsoutput current to below the positive output current reference. Inanother embodiment, controlling output voltage of the converter to anoutput voltage reference, controlling output power of the converter tothe positive power reference, and controlling output power of theconverter to the negative power reference include using one or moreouter feedback control loops to the current feedback control loop, whichforms an inner feedback control loop. In another embodiment, limitingoutput current to a positive output current reference includesgenerating one or more output control signals that vary over a pluralityof control regions, where each control region includes a differentcompensation equation. In another embodiment, the method includesvarying the output voltage reference with output current such that theoutput voltage reference decreases as output current increases, wherethe output voltage reference varies based on the equation:V _(Set)(I _(O))=V _(Set)(0)−I _(OUT) R _(V)

-   -   where:    -   V_(Set) (I_(O)) is the output voltage reference as a function of        output current;    -   V_(Set) (0) is the output voltage reference at zero output        current;    -   R_(V) is a resistance representing a slope of the output voltage        reference; and    -   I_(OUT) is output current of the converter.

In another embodiment, the method includes varying the positive outputcurrent reference with output voltage such that the positive outputcurrent reference decreases as output voltage increases, where thepositive output current reference varies based on the equation:

${I_{Set}\left( V_{OUT} \right)} = {{I_{Set}(0)} - \frac{V_{OUT}}{R_{I}}}$

-   -   where:    -   I_(Set) (V_(OUT)) is the positive output current reference as a        function of output voltage;    -   I_(Set) (0) is the positive output current reference at zero        output voltage;    -   V_(OUT) is the output voltage; and    -   R_(I) is a resistance representing a slope of the positive        output current reference.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the advantages of the invention will be readilyunderstood, a more particular description of the invention brieflydescribed above will be rendered by reference to specific embodimentsthat are illustrated in the appended drawings. Understanding that thesedrawings depict only typical embodiments of the invention and are nottherefore to be considered to be limiting of its scope, the inventionwill be described and explained with additional specificity and detailthrough the use of the accompanying drawings, in which:

FIG. 1 is a schematic block diagram illustrating one embodiment of a DCto DC converter;

FIG. 2A is a schematic diagram illustrating one embodiment of a resonantpower converter;

FIG. 2B is a schematic diagram illustrating another embodiment of aresonant power converter;

FIG. 2C is a schematic diagram illustrating one alternate embodiment ofa resonant power converter;

FIG. 3 is a schematic block diagram illustrating one embodiment of adigital signal conditioning module;

FIG. 4 is a schematic block diagram of a switching leg and associatedtiming diagram;

FIG. 5 is a schematic block diagram of a full bridge switching networkand timing diagrams;

FIG. 6 is a schematic diagram of a full bridge switch networkrepresented as an equivalent transformer;

FIG. 7 is a phasor transformer model of a full bridge switch networkwith associated left-to-right voltage conversion and right-to-leftcurrent conversion ratios;

FIG. 8 is a phasor model of the Dual Active Bridge Series ResonantConverter;

FIG. 9 is a general small signal model of a full bridge switch networkrepresented as an equivalent transformer;

FIG. 10 is a small signal equivalent tank impedance for the DABSRC;

FIG. 11 depicts MCT (solid curve) and normalized RMS tank currentcontours (a) on the φ_(DC)=π plane for M=0.5 and (b) on the φ_(AB)=πplane for M=1.5;

FIG. 12 depicts phasor diagrams in forward power mode along the MCT, M<1case along branches γ₁₊/γ¹⁻ (a) and along branch γ₂ (b);

FIG. 13 depicts theoretical hard switching vs. soft switching boundaryfor the input bridge in the M<1 case: comparison between one-anglemodulation and minimum current trajectory;

FIG. 14 depicts output command to output current transfer functionsplotted for a sweep from 90% reverse power to 90% forward power;

FIG. 15 is a schematic block diagram of a gain scheduled feedback loopfor output current control;

FIG. 16 depicts Gain Schedule for a V_(IN)=500 V DABSRC derived formaximum converter bandwidth at all points;

FIG. 17 depicts Gain Schedule phase margin for a V_(IN)=500 V DABSRCderived for maximum converter bandwidth at all points;

FIG. 18 depicts (a) multi-mode control output plane detailing of power,current, and voltage limit curves for a bidirectional converter, and (b)modified limit curves to enable inherent power, voltage, and currentsharing;

FIG. 19 is a schematic block diagram of one embodiment of a multi-modecontrol (“MMC”) control loops showing a current regulated converter withan internal current feedback loop, as well as a power and voltage outerfeedback loops;

FIG. 20 depicts a voltage regulation loop for multi-mode control of theDABSRC;

FIG. 21 is a schematic block diagram of a linearized power regulationloop for multi-mode control of the DABSRC;

FIG. 22 depicts half-bridge switching where switches Q₁ and Q₂ areassumed to operate at a fixed frequency, f_(s);

FIG. 23 is a schematic block diagram of one embodiment of a PSMhalf-bridge consisting of switches Q₁′ and Q₂′ connected to an existingconverter half-bridge (Q₁ and Q₂) through auxiliary inductor L_(aux) foractive ZVS assistance of Q₁ and Q₂;

FIG. 24 depicts phase shift modulated half-bridge (“PSM-HB”) waveforms,showing ZVS assistance current flowing in the correct direction for ZVSat both Q₁ and Q₂ turn on;

FIG. 25 is a schematic block diagram of a PSM-HB integration circuit fordirect measurement of charge delivered during the dead time betweenswitching events;

FIG. 26 depicts a simple PSM-HB modulation (a) that applies phase anglechanges in a single step, introducing non-zero average auxiliarycurrent;

FIG. 27 is a schematic block diagram of one embodiment of a control loopblock diagram for the PSM-HB;

FIG. 28 depicts PSM-HB control to output closed loop transfer function;

FIG. 29 is a schematic block diagram of one embodiment of a PSM-HBfeedback circuit, incorporating bridge voltage V_(A) dependent tablesfor charge reference Q_(REF) and minimum phase shift Φ_(Min);

FIG. 30 is a schematic block diagram of one embodiment of a DC to DCconverter with two parallel DABSRC stages;

FIG. 31 depicts Phase shift modulation and definition of control anglesfor each DABSRC stage;

FIG. 32 depicts one example of normalized active power contours on theφ_(DC)=180° plane, minimum current trajectory for M=0.5 andcorresponding separation between capacitive and inductive reactive powerregions;

FIG. 33 depicts one example of normalized active power contours on theφ_(DC)=180° plane; the minimum current trajectory and a particular ZVStrajectory are shown for M=0.5, together with two correspondingoperating points A_(MCT);

FIG. 34 are tank phasor diagrams for Q_(DC)=0 (a) and on a generic ZVStrajectory (b);

FIG. 35 depicts normalized input turn-off currents for leg B vs.normalized active power level along three different ZVS trajectories,M=0.5;

FIG. 36 depicts input ZVS operation via phase-shift between the twoDABSRC stages: main waveforms;

FIG. 37 illustrates the worst-case auxiliary currentI_(aux,max)—normalized to the full-power tank current amplitude—thatneeds to be injected at input nodes A/B in order to guaranteemin(i_(A↓), i_(B↓))≧0;

FIG. 38 is a computation flowchart for FPGA based MCT calculation;

FIG. 39 depicts logic statements needed to combine partial phase anglesinto final control angles;

FIG. 40 is a direct form I implementation of the output current feedbackcontroller;

FIG. 41 is a schematic block diagram of a ZVS controller implementedwith two lookup tables for Φ_(Min) and Q_(REF);

FIG. 42 is a ZVS lookup table connections for Φ_(Min) and Q_(REF);

FIG. 43 is a schematic block diagram of a single pole controllerimplementation for a cascaded two pole MMC controller;

FIG. 44 is a schematic block diagram of one embodiment of a MMC voltagecontroller error generation including droop resistance;

FIG. 45 is a schematic block diagram of one embodiment of a MMC powercontroller error generation;

FIG. 46 is a schematic block diagram of one embodiment of currentreference selection logic for MMC;

FIG. 47 FIG. 47 depicts an experimental step response of the DABSRC tankcurrent compared to the model;

FIG. 48 depicts simulated function

with Φ_(DC)=180°, and Φ_(AD)=90°;

FIG. 49 depicts simulated function

with Φ_(AB)=180°, and Φ_(DC)=180°;

FIG. 50 depicts simulated function

with Φ_(AB)=180°, and Φ_(AD)=90°;

FIG. 51 depicts simulated function H_(i) _(o) ^(ab) with Φ_(DC)=180°,and Φ_(AD)=90°;

FIG. 52 depicts H_(i) _(o) ^(ab) with Φ_(AB)=180°, and Φ_(DC)=180°;

FIG. 53 depicts simulated function H_(i) _(o) ^(dc) with Φ_(AB)=180°,and Φ_(AD)=90°;

FIG. 54 depicts simulated RMS tank current, M=0.5 example;

FIG. 55 depicts turn-off currents of input devices Q₁/Q₂ (a) and Q₃/Q₄(b) versus the output power, M=0.5 example;

FIG. 56 reports the simulated turn-off currents of output devices Q₅ . .. Q₈;

FIG. 57 displays experimental waveforms at 1.1 kW forward power,V_(g)=500V, V_(out)=400V, M=1; voltage scale: 250V/div; current scale: 2A/div; time scale: 2 μs/div;

FIG. 57 reports the experimental tank current and voltages v_(AB)(t) andv_(DC)(t) for a 1.1 kW forward power operating point, at which themeasured efficiency was 96%;

FIG. 58 depicts experimental efficiency at nominal voltage levelsV_(g)=500 V, V_(out)=400 V, M=1;

FIG. 59 depicts experimental vs. analytical power flow (a) and RMS tankcurrent distribution (b), V_(g)=200V, V_(out)=80V, M=0.5;

FIG. 60 illustrates such comparison in terms of RMS tank current versusoutput power;

FIG. 61 depicts experimental efficiency: minimum current trajectory vs.one-angle modulation, M=0.5, V_(IN)=200 V, V_(OUT)=80 V;

FIG. 62 depicts experimental turn-off currents on leg D (a) and leg B(b): minimum current trajectory vs. one-angle modulation, M=0.5,V_(IN)=200 V, V_(OUT)=80 V;

FIG. 63 depicts experimental waveforms relative to minimum currentoperation at V_(IN)=500 V, V_(OUT)=200 V, P_(OUT)=160 W;

FIG. 64 depicts experimental data where V_(A)=130 V, soft start usingPSM-HB ZVS assistance;

FIG. 65 depicts experimental data where V_(A)=130 V, ZVS operationsusing PSM-HB assistance;

FIG. 66 depicts experimental results where V_(A)=130V, ZVS operationsusing PSM-HB assistance;

FIG. 67 depicts experimental results where V_(A)=130 V, ZVS operationsusing PSM-HB assistance;

FIG. 68 depicts experimental waveforms for full ZVS operation with theproposed technique, P_(test)=110 W; voltage scale: 250V/div; currentscale: 2 A/div; time scale: 2 μs/div;

FIG. 69 depicts experimental efficiency of the DC/DC unit with theconventional one-angle modulation and with the proposed ZVS technique;

FIG. 70 depicts experimental input and output turn-off currents alongthe selected ZVS trajectory;

FIG. 71 depicts experimental data with M=0.5 and a constant gaincontroller is compared with a gain-scheduled controller;

FIG. 72 depicts experimental data for an output current step response,M=1.0, I_(SET)=1.25 A stepped to I_(SET)=2.10 A, V_(IN)=300 V;

FIG. 73 includes experimental data for a gain-scheduled feedbackcontroller gain profile, M=1.0, I_(SET)=1.25 A stepped to I_(SET)=2.10A, V_(IN)=300 V;

FIG. 74 depicts simulation results for normalized output variables fortwo series output connected converters;

FIG. 75 depicts simulation results for normalized output variables fortwo parallel output connected converters;

FIG. 76 depicts simulation results for normalized output variables fortwo parallel output connected converters;

FIG. 77 depicts simulation results for normalized output variables fortwo series output connected converters;

FIG. 78 depicts normalized output variables for two parallel outputconnected converters;

FIG. 79 is a schematic block diagram of one embodiment of a multi-modecontrol apparatus in accordance with one embodiment of the invention;

FIG. 80 is a schematic flowchart diagram illustrating one embodiment ofa method 8000 for multi-mode control;

FIG. 81 is a schematic flowchart diagram illustrating another embodimentof a method 8100 for multi-mode control;

FIG. 82 is a schematic flowchart diagram illustrating another embodimentof a method 8200 for assisted ZVS;

FIG. 83 is a schematic block diagram of one embodiment of a modified MCTapparatus 8300 in accordance with one embodiment of the presentinvention;

FIG. 84 is a schematic block diagram of another modified ZVS apparatus8400 according to one embodiment of the present invention;

FIG. 85 is a schematic flowchart diagram illustrating an embodiment of amethod 8500 for modified MCT control; and

FIG. 86 is a schematic flowchart diagram illustrating another embodimentof a method 8600 for modified MCT control.

DETAILED DESCRIPTION

Reference throughout this specification to “one embodiment,” “anembodiment,” or similar language means that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least one embodiment. Thus, appearances of the phrases“in one embodiment,” “in an embodiment,” and similar language throughoutthis specification may, but do not necessarily, all refer to the sameembodiment, but mean “one or more but not all embodiments” unlessexpressly specified otherwise. The terms “including,” “comprising,”“having,” and variations thereof mean “including but not limited to”unless expressly specified otherwise. An enumerated listing of itemsdoes not imply that any or all of the items are mutually exclusiveand/or mutually inclusive, unless expressly specified otherwise. Theterms “a,” “an,” and “the” also refer to “one or more” unless expresslyspecified otherwise.

Furthermore, the described features, advantages, and characteristics ofthe embodiments may be combined in any suitable manner. One skilled inthe relevant art will recognize that the embodiments may be practicedwithout one or more of the specific features or advantages of aparticular embodiment. In other instances, additional features andadvantages may be recognized in certain embodiments that may not bepresent in all embodiments.

These features and advantages of the embodiments will become more fullyapparent from the following description and appended claims, or may belearned by the practice of embodiments as set forth hereinafter. As willbe appreciated by one skilled in the art, aspects of the presentinvention may be embodied as a system, method, and/or computer programproduct. Accordingly, aspects of the present invention may take the formof an entirely hardware embodiment, an entirely software embodiment(including firmware, resident software, micro-code, etc.) or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a “circuit,” “module,” or “system.”Furthermore, aspects of the present invention may take the form of acomputer program product embodied in one or more computer readablemedium(s) having program code embodied thereon.

Many of the functional units described in this specification have beenlabeled as modules, in order to more particularly emphasize theirimplementation independence. For example, a module may be implemented asa hardware circuit comprising custom VLSI circuits or gate arrays,off-the-shelf semiconductors such as logic chips, transistors, or otherdiscrete components. A module may also be implemented in programmablehardware devices such as field programmable gate arrays, programmablearray logic, programmable logic devices or the like.

Modules may also be implemented in software for execution by varioustypes of processors. An identified module of program code may, forinstance, comprise one or more physical or logical blocks of computerinstructions which may, for instance, be organized as an object,procedure, or function. Nevertheless, the executables of an identifiedmodule need not be physically located together, but may comprisedisparate instructions stored in different locations which, when joinedlogically together, comprise the module and achieve the stated purposefor the module.

Indeed, a module of program code may be a single instruction, or manyinstructions, and may even be distributed over several different codesegments, among different programs, and across several memory devices.Similarly, operational data may be identified and illustrated hereinwithin modules, and may be embodied in any suitable form and organizedwithin any suitable type of data structure. The operational data may becollected as a single data set, or may be distributed over differentlocations including over different storage devices, and may exist, atleast partially, merely as electronic signals on a system or network.Where a module or portions of a module are implemented in software, theprogram code may be stored and/or propagated on in one or more computerreadable medium(s).

The computer program product may include a computer readable storagemedium (or media) having computer readable program instructions thereonfor causing a processor to carry out aspects of the present invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (“RAM”), aread-only memory (“ROM”), an erasable programmable read-only memory(“EPROM” or Flash memory), a static random access memory (“SRAM”), aportable compact disc read-only memory (“CD-ROM”), a digital versatiledisk (“DVD”), a memory stick, a floppy disk, a mechanically encodeddevice such as punch-cards or raised structures in a groove havinginstructions recorded thereon, and any suitable combination of theforegoing. A computer readable storage medium, as used herein, is not tobe construed as being transitory signals per se, such as radio waves orother freely propagating electromagnetic waves, electromagnetic wavespropagating through a waveguide or other transmission media (e.g., lightpulses passing through a fiber-optic cable), or electrical signalstransmitted through a wire.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (“ISA”) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on a computer, partlyon the computer, as a stand-alone software package, partly on thecomputer and partly on a remote computer or entirely on the remotecomputer or server. In the latter scenario, the remote computer may beconnected to the user's computer through any type of network, includinga local area network (LAN) or a wide area network (WAN), or theconnection may be made to an external computer (for example, through theInternet using an Internet Service Provider). In some embodiments,electronic circuitry including, for example, programmable logiccircuitry, field-programmable gate arrays (“FPGA”), or programmablelogic arrays (“PLA”) may execute the computer readable programinstructions by utilizing state information of the computer readableprogram instructions to personalize the electronic circuitry, in orderto perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be implemented inhardware, may be provided to a processor of a general purpose computer,special purpose computer, or other programmable data processingapparatus to produce a machine, such that the instructions, whichexecute via the processor of the computer or other programmable dataprocessing apparatus, create means for implementing the functions/actsspecified in the flowchart and/or block diagram block or blocks. Thesecomputer readable program instructions may also be stored in a computerreadable storage medium that can direct a computer, a programmable dataprocessing apparatus, and/or other devices to function in a particularmanner, such that the computer readable storage medium havinginstructions stored therein comprises an article of manufactureincluding instructions which implement aspects of the function/actspecified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

Although various arrow types and line types may be employed in theflowchart and/or block diagrams, they are understood not to limit thescope of the corresponding embodiments. Indeed, some arrows or otherconnectors may be used to indicate only the logical flow of the depictedembodiment. For instance, an arrow may indicate a waiting or monitoringperiod of unspecified duration between enumerated steps of the depictedembodiment. It will also be noted that each block of the block diagramsand/or flowchart diagrams, and combinations of blocks in the blockdiagrams and/or flowchart diagrams, can be implemented by specialpurpose hardware-based systems that perform the specified functions oracts, or combinations of special purpose hardware and program code.

I. Definitions and Notation

Full signal quantities are defined as the sum of both large signal(generally constant) portions of a signal as well as the time varyingsmall signal portion. Lower case letters with capital subscripts areused to represent these full signal quantities,i _(T) =I _(T) +ĩ _(t),  (1)where the large signal component is represented using a capital letterand a capital subscript. The small signal portion of a signal isrepresented using both lowercase letters and subscripts with theaddition of a tilde. Time domain signals use parenthesis, as inv_(IN)(t) for the time varying signal ‘v_(IN)’, while frequency domainsignals are represented by their Fourier series coefficients usingsquare brackets and an over-hat. Using this notation the signalv_(IN)(t) would be represented by its Fourier series coefficients as{circumflex over (v)}_(IN)[n] in the frequency domain. Phasor signalsare represented with an over-bar, such that phasor s _(X) satisfiess _(X)(t,ω _(s))=Re[s _(X) e ^(+ω) ^(s) ^(t)].  (2)

The frequency that a phasor exists in is determined either by thecontext of the specific derivation or by an explicit statement. Phasorsat zero frequency are assumed to exist and are equivalent to constantquantities such that the DC voltage v_(IN)=v _(IN).

Complex quantifies use the variable ‘j’ to represent the complexvariable. Double bars are used to represent the magnitude of complexquantities, with an angle symbol representing phase. Additionally theuse of a super script ‘*’ represents the complex conjugate of a number,while a ‘*’ used between elements designates convolution. Super scriptsare used to designate the parameter with which a quantity has beenderived in respect to. Finally, angled brackets are used for normalizedvalues with a possible subscript to designate the normalizing quantity.Digitized signals may be represented as underlined symbols, e.g. thedigitized output voltage V_(OUT) is V _(OUT), which may be usedinterchangeably with V_(OUT).

II. Converter Topologies and the DABSRC

Due to the many demonstrated advantages of a dual active bridge seriesresonant converter (“DABSRC”), a DABSRC topology is selected for thiswork. This typically topology provides high efficiency and good powerdensity for the 1 kW, 500 V target operating range. Additionally, theDABSRC is a well-known converter which provides input/output isolationand bidirectional power flow. Other topologies may also be used withregard the embodiments of the proposed invention described herein.

II.1 Overall System

FIG. 1 is a schematic block diagram illustrating one embodiment of adirect current (“DC”) to DC converter 10. The DC to DC converter 10includes a resonant power converter 100, a digital signal conditioningmodule 205, a main power flow controller 215, and a modulator 290. Inaddition, the DC to DC converter 10 may include a master controller 295.In one embodiment, the converter 10 may power an electronic device, suchas a laptop computer, a music player, a tablet and the like. Theconverter may also provide power from a source to a battery where thebattery then provides power to a load through the converter 10 where thesource is disconnected and the load is connected. For example, theconverter 10 may provide power to charge a battery of an electricvehicle and then may provide power in a reverse direction through theconverter 10 to the electric vehicle.

In one embodiment, the resonant power converter 100 is a DABSRC, as willbe shown hereafter. Alternatively, the resonant power converter 100 maybe a half bridge resonant converter as will be shown hereafter. In otherembodiments, the resonant power converter 100 may include other resonantconverter topologies. The resonant power converter 100 receives gatedrive signals 110 from the modulator 290 and in response to the gatedrive signals 110 converts an input DC voltage to an output DC voltageas will be described hereafter. The resonant power converter 100 mayhave a sensed output voltage V_(OUT), a sensed input voltage V_(IN), asensed output current I_(OUT), and a sensed input current I_(IN). One ormore sensors may measure the sensed output voltage V_(OUT), the sensedinput voltage V_(IN), the sensed output current I_(OUT), and the sensedinput current I_(IN). The sensed output voltage V_(OUT), the sensedinput voltage V_(IN), the sensed output current I_(OUT), and the sensedinput current I_(IN) may be digital or analog signals.

In one embodiment, the digital signal conditioning module 205 receivesthe sensed output voltage V_(OUT), sensed input voltage V_(IN), sensedoutput current I_(OUT), and sensed input current I_(IN) and generatesdigital representations converter output voltage V _(OUT), an converterinput voltage V _(IN), an converter output current I _(OUT), and anconverter input current I _(IN) as will be described hereafter. In oneembodiment, the converter output voltage V _(OUT), the converter inputvoltage V _(IN), the converter output current I _(OUT), and theconverter input current I _(IN) are equivalent to the sensed outputvoltage V_(OUT), the sensed input voltage V_(IN), the sensed outputcurrent I_(OUT), and the sensed input current I_(IN) respectively. Theconverter output voltage V _(OUT), the converter input voltage V _(IN),the converter output current I _(OUT), and the converter input current I_(IN) may be digital signals.

The main power flow controller 215 may receive the converter outputvoltage V _(OUT), the converter input voltage V _(IN), the converteroutput current I _(OUT), and the converter input current I _(IN). Inaddition, the main power flow controller 215 may receive referencesignals such as a power reference P_(SET), a voltage reference V_(SET),and a current reference I_(SET). The master controller 295 may generatethe power reference P_(SET), voltage reference V_(SET), and currentreference I_(SET).

The main power flow controller 215 may generate control signals 280 thatdrive a plurality of phase shift modulators 230 of the modulator 290 togenerate the gate drive signals 110 that operate the resonant powerconverter 100. The main power flow controller 215 may operate theresonant power converter 100 with a resonant tank current equal to adynamic target resonant current. The dynamic target resonant current maybe selected to minimize the resonant tank current. In one embodiment,the dynamic target resonant current is selected to minimize the resonanttank current while achieving a desired resonant converter output power.In a certain embodiment, the dynamic target resonant current is selectedto satisfy (3):

$\begin{matrix}{\min_{v_{\varphi} \in C_{s}}{{{I_{{RM}\; S}\left( v_{\varphi} \right)}}\text{:}\left\{ \begin{matrix}{{P_{o}\left( v_{\varphi} \right)} = {\overset{\_}{P}}_{o}} \\{{- P_{o,{{ma}\; x}}} \leq {\overset{\_}{P}}_{o} \leq {+ P_{o,{{ma}\; x}}}}\end{matrix} \right.}} & (3)\end{matrix}$

In one embodiment, each phase shift modulator 230 of the modulator 290generates 50% duty cycle square wave pulses that control thesemiconductor switches 105. The functions of the elements of the DC toDC converter 10 are described hereafter.

II.2 DABSRC Description

FIG. 2A is a schematic diagram illustrating one embodiment of theresonant power converter 100. In the depicted embodiment, the resonantpower converter 100 is a DABSRC. A voltage applied to an input 141 maybe converted to a desired voltage at an output 143. The sensed inputvoltage V_(IN) and the sensed input current I_(IN) may be measured byone or more sensors at the input 141. In addition, the sensed outputvoltage V_(OUT) and the sensed output current I_(OUT) may be measured byone or more sensors at the output 143.

The resonant power converter 100 includes a plurality of semiconductorswitches 105 and a resonant tank 155. Each semiconductor switch 105 isactivated and deactivated in response to a gate drive signal 110.

In the depicted embodiment, the resonant tank 155 includes an inductorL_(R), a capacitor C_(R), and a transformer 120. The gate drive signals110 activate and deactivate first switches 111 to generate analternating voltage and a resonant tank current 257 across the resonanttank 155. The gate drive signals 110 further activate and deactivatesecond switches 112 to rectify the alternating voltage and generate adesired DC voltage at the output 143.

FIG. 2B is a schematic diagram illustrating one alternate embodiment ofa resonant power converter 101. In the depicted embodiment, the resonantpower converter 101 is a variation of the resonant converter depicted inFIG. 2A. The inductor L_(R) is split between the positive and negativelegs of the resonant tank 155 and the capacitor C_(R) is also split. Thevalues of the inductors and capacitors are chosen to be equivalent tothe values of the inductor and capacitor in the resonant converter 100of FIG. 2A.

FIG. 2C is a schematic diagram illustrating another alternate embodimentof a resonant power converter 102. In the depicted embodiment, theresonant converter 102 is a half bridge resonant converter. As in FIG.2A, for the resonant converters 101, 102 of FIGS. 2B and 2C, a voltageapplied to an input 141 may be converted to a desired voltage at anoutput 143. The sensed input voltage V_(IN) and the sensed input currentI_(IN) may be measured by sensors at the input 141. In addition, thesensed output voltage V_(OUT) and the sensed output current I_(OUT) maybe measured by sensors at the output 143. The resonant power converter100 includes a plurality of semiconductor switches 105 and a resonanttank 155. Each semiconductor switch 105 is activated and deactivated inresponse to gate drive signal 110.

In the depicted embodiments, the resonant tank 155 includes an inductorL_(R) and a capacitor C_(R). The gate drive signals 110 activate anddeactivate first switches 111 to generate an alternating voltage and aresonant tank current 257 across the resonant tank 155. The gate drivesignals 110 further activate and deactivate second switches 112 torectify the alternating voltage and generate a desired DC voltage at theoutput 143.

In order to achieve a high bandwidth output current control, a new modelfor the DABSRC is derived based on the phasor analysis and equivalenttransformer work previously developed. This new model is used to derivecontrol to output transfer functions for the DABSRC, and exposes thehigh degree of variability in control to output gain based on converteroperating point experienced in the topology. Because the converter beingdesigned must operate over a wide range of both power levels andconversion rations, a gain scheduled approach may be used for feedbackregulation of output current.

A fixed frequency phase shift modulated switching method is selected forthe DABSRC. By adopting the MCT approach, RMS tank currents I_(T) arekept to a minimum, thus increasing overall converter efficiency.Although a number of other switching methods are possible, the MCTapproach lends itself well to variable conversion ratio application.

In order to achieve soft switching of the DABSRC over the wide range ofoperating conditions required by this application, a PSM auxiliary legapproach is taken. This method is used without the DC blockingcapacitors typically employed, based on work showing that in certaincases inductively linked half bridges do not require the DC blockingcapacitors.

FIG. 3 is a schematic block diagram illustrating one embodiment of thedigital signal conditioning module 205. The digital signal conditioningmodule 205 receives the sensed output voltage V_(OUT), sensed inputvoltage V_(IN), sensed output current I_(OUT), and sensed input currentI_(IN) and generates the converter output voltage V _(OUT), converterinput voltage V _(IN), converter output current I _(OUT), and converterinput current I _(IN). The digital signal conditioning module 205includes an outlier detection/removal module 610, a data averagingmodule 615, and an offset removal module 620.

The outlier detection/removal module 610 may filter out spurioussignals, noise, and other outlier values from the sensed output voltageV_(OUT), sensed input voltage V_(IN), sensed output current I_(OUT), andsensed input current I_(IN). The data averaging module 615 may calculatea moving average for each of the sensed output voltage V_(OUT), sensedinput voltage V_(IN), sensed output current I_(OUT), and sensed inputcurrent I_(IN). The offset removal module 620 may remove value offsetsand/or signal bias from each of the sensed output voltage V_(OUT),sensed input voltage V_(IN), sensed output current I_(OUT), and sensedinput current I_(IN) to generate the converter output voltage V _(OUT),converter input voltage V _(IN), converter output current I _(OUT), andconverter input current I _(IN).

III Modeling the DABSRC

In order to achieve a high bandwidth output current regulation, a newmodel for the DABSRC is developed. The model sought relates each of thethree possible control angles for the DABSRC independently to both theinput and output currents of the converter. The derivation begins withan analysis of the active bridge switch network. This analysis leads tothe equivalent transformer as a way to linearize the effects of theswitch network. This linearization enables the use of common circuitanalysis techniques in order to derive the desired control to outputrelations for the DABSRC.

III.1 The Equivalent Transformer in Steady State

The equivalent transformer allows active switch networks in powerconverters to be replaced with a “transformer” model with a time varyingconversion ratio. When the equivalent transformer is constrained to asingle frequency it is the same as the phasor transformer, and performsthe function of converting DC waveforms into phasor waveforms. Thisprocess is equivalent to using fundamental analysis to solve a circuitalthough graphically it tends to be more intuitive. The derivation ofthe full equivalent transformer model begins with harmonic analysis of ageneral half bridge switch network. This analysis leads to the fullequivalent transformer model, which is then simplified to the phasortransformer.

FIG. 4 is a schematic block diagram of a switching leg and associatedtiming diagram. The switch node voltage of a pair of switches setup asin FIG. 4 can be defined as a piecewise linear function of the bridgevoltage v₁, the dead-time t_(d), the switching period T_(s), and theduty cycle d. For the remainder of this section, v₁ is assumed to beconstant, t_(d) is assumed much smaller than the constant switchingperiod T_(s), and duty cycle d is assumed to operate at a fixed value of½. Although the switch node voltage during the dead time is unknown, itcan in general be assumed symmetric around ½v₁ for rising and fallingtransitions. Under this assumption, the shape of the voltage during thedead-time does not affect the average value of the switch node voltageover integer multiples of switching period T_(s). The most noticeableeffect of the dead-time in this case is a small phase shift in theswitch node output voltage frequency spectrum which ranges from ½t_(d)lead to ½t_(d) lag. As most systems operate somewhere in between theselimits with small dead-times, this effect will be ignored and harmonicanalysis will proceed without the small dead-time phase shift taken intoaccount.

FIG. 5 is a schematic block diagram of a full bridge switching networkand timing diagrams. Assuming zero dead-time, the switch node outputvoltages v_(A) and v_(B) of FIG. 5 can be defined in general as theinfinite series

$\begin{matrix}{{v_{sw}\left( {t,\varphi} \right)} = {\sum\limits_{n = {- \infty}}^{+ \infty}{{{\hat{v}}_{sw}\left\lbrack {n,\varphi} \right\rbrack}{\mathbb{e}}^{{j\omega}_{s}n\; t}}}} & (4) \\{{{{\hat{v}}_{sw}\left\lbrack {n,\varphi} \right\rbrack} = {\frac{\omega_{s}}{2\pi}{\int_{0}^{\frac{2\pi}{\omega_{s}}}{{v_{sw}\left( {t,\varphi} \right)}{\mathbb{e}}^{{- j}\;\omega_{s}n\; t}{\mathbb{d}t}}}}},} & (5)\end{matrix}$where (5) represents the complex valued Fourier Series coefficients of(4) and angular switching frequency ω_(s)=2π/T_(s). Using (5) torepresent the switch node voltage of a single half-bridge in thefrequency domain the output voltage of a full-bridge switch network canbe defined as the difference of two such series,

$\begin{matrix}\begin{matrix}{{{\hat{v}}_{2}\lbrack n\rbrack} = {{{\hat{v}}_{sw}\left\lbrack {n,\varphi_{A}} \right\rbrack} - {{\hat{v}}_{sw}\left\lbrack {n,\varphi_{B}} \right\rbrack}}} \\{= {{{\hat{v}}_{A}\lbrack n\rbrack} - {{\hat{v}}_{B}\lbrack n\rbrack}}} \\{= \left\{ {\begin{matrix}{\frac{v_{1}{\mathbb{e}}^{{- j}\; n\;\varphi_{A}}}{j\; n\;\pi}\left( {1 - {\mathbb{e}}^{{- j}\; n\;\varphi_{AB}}} \right)} & {{n \neq 0},{even}} \\0 & {else}\end{matrix},} \right.}\end{matrix} & (6)\end{matrix}$with phase angles φ_(A) and φ_(AB) allowing phase shift modulatedcontrol of the full bridge network as seen in FIG. 5. Angle φ_(A) isunconstrained, while angle φ_(AB) is constrained to the region between 0and π. Angles of φ_(AB) between −π and 0 are obtained by applying a πdegree phase shift to (5). With this in mind the original constraintdoes not reduce the generality of the approach while greatly simplifyingthe following derivations. By normalizing (6) with respect to the inputbridge voltage v₁ a voltage independent series is defined

$\begin{matrix}{{{\hat{s}}_{N}\lbrack n\rbrack} = \left\{ {\begin{matrix}{\frac{{\mathbb{e}}^{{- j}\; n\;\varphi_{A}}}{j\; n\;\pi}\left( {1 - {\mathbb{e}}^{{- j}\; n\;\varphi_{AB}}} \right)} & {{n \neq 0},{even}} \\0 & {else}\end{matrix}.} \right.} & (7)\end{matrix}$

Series (7) relates the input and output voltage of the full bridgeswitch network in the same way as a transformer turns-ratio relatesinput and output voltages of an ideal transformer. For this reason it isdefined as the “equivalent turns-ratio” of the full bridge switchnetwork. As the reciprocal of (7) is not well defined in this form, theequivalent transformer only allows voltages to be computed from input tooutput, and current to be computed from output to input when stated inthis way.

The output current of the full bridge switch network can be described asits own seriesî ₂ [n]=k ₂ [n]e ^(jφ) ² ^([n])  (8)where phase shift φ₂ and gain k₂ are dependent on the impedance seen bythe full bridge output and thus unknown. In a conventional transformerthe output current (8) would be multiplied by turns ratio (7) in orderto determine the input current. By using a discrete convolution in placeof simple multiplication this is still the case in the frequency domainfor the equivalent transformer,

$\begin{matrix}\begin{matrix}{{{\hat{i}}_{1}\lbrack n\rbrack} = {{{\hat{s}}_{N}\lbrack n\rbrack}*{{\hat{i}}_{2}\lbrack n\rbrack}}} \\{= {\sum\limits_{x = {- \infty}}^{+ \infty}{{{\hat{s}}_{N}\left\lbrack {n + x} \right\rbrack}{{{\hat{i}}_{2}\left\lbrack {- x} \right\rbrack}.}}}}\end{matrix} & (9)\end{matrix}$

Applying the definition of convolution seen in (9) to the full bridge NZ voltage relation as well, a symmetrical set of equations can be usedto describe a full bridge switch networks voltage and current conversionratios,î ₁ [n]=ŝ _(N) [n]*î ₂ [n],  (10){circumflex over (v)} ₂ [n]=ŝ _(N) [n]*{circumflex over (v)} ₁[n].  (11)

Equations (10) and (11) represent the voltage and current conversionsperformed by a full bridge switch network in a form similar to that of atraditional transformer, and allow such networks to be replaced withequivalent transformer models in the frequency domain.

To ease calculations the infinite series in (10) and (11) are commonlyreplaced with finite approximations. This can be done by selecting aninteger N such that

$\begin{matrix}{{{f(t)} = {{\sum\limits_{n = {- N}}^{+ N}{{\hat{f}\lbrack n\rbrack}{\mathbb{e}}^{j\;\omega_{s}n\; t}}} + ɛ}},} & (12)\end{matrix}$where the truncation error ε has a computable upper bound and can bemade arbitrarily small with larger values of N. As the magnitude ofhigher harmonics drops off sharply, (12) is an acceptable approximationfor even small values of N. These two factors allow truncation error εto be ignored for most practical choices of N, resulting in a finiteseries representation for f(t) in the frequency domain using only asmall number of Fourier series coefficients.

To ensure that harmonics above N are not reintroduced to the systemthrough multiplication, a truncated form of discrete convolution isintroduced,

$\begin{matrix}\begin{matrix}{{\hat{g}\lbrack n\rbrack} = {{\hat{f}\lbrack n\rbrack}*{\hat{h}\lbrack n\rbrack}}} \\{= \left\{ {\begin{matrix}{\sum\limits_{x = {- N}}^{n + N}{{\hat{f}\lbrack x\rbrack}{\hat{h}\left\lbrack {n - x} \right\rbrack}}} & {n \in \left\lbrack {{- N},0} \right\rbrack} \\{\hat{g}\left\lbrack {- n} \right\rbrack}^{*} & {else}\end{matrix}.} \right.}\end{matrix} & (13)\end{matrix}$

This truncation is similar to assuming that a system does not existabove frequencies indexed by N, which is a common simplification whenmodeling converters. By substituting truncated series for all voltagesand currents in (10) and (11) and using (13) for convolution, a finiteseries approximation of the equivalent transformer is defined. FIG. 6 isa schematic diagram of a full bridge switch network represented as anequivalent transformer. The same circuit as seen in FIG. 5 isrepresented. This equivalent transformer is represented in FIG. 6 as anarbitrarily accurate substitution for the full bridge switch network inFIG. 5.

In many systems approximating complex waveforms with their fundamentalharmonic is accurate enough to allow meaningful results without overlycomplicated computation. This is easily achieved with the equivalenttransformer model by setting N=1 in (12) and (13). Selecting this valuefor N allows many simplifications and results in the “phasortransformer” model of a full bridge switch network. This form of theequivalent transformer has previously been used to analyze time varyingcircuits and is derived here for use in resonant converters as a subsetof the equivalent transformer. Although some of the final equationsreached in this section have previously been seen, their relation to thefull frequency content of converter signals has been neglected untilnow.

Because current i₂ and turns ratio s_(N) both have zero average valueand represent real-valued waveforms, (10) can be simplified into

$\begin{matrix}{{{\hat{i}}_{1}\lbrack n\rbrack} = \left\{ {\begin{matrix}{2{{Re}\left\lbrack {{{\hat{s}}_{N}\left\lbrack {+ 1} \right\rbrack}^{*}{{\hat{i}}_{2}\left\lbrack {+ 1} \right\rbrack}} \right\rbrack}} & {n = 0} \\0 & {else}\end{matrix}.} \right.} & (14)\end{matrix}$

Due to the relationship between a real signal's fundamental frequencyphasor representation and its Fourier coefficients,g=2ĝ[+1]  (15)where g is the phasor representation of g(t) at frequency ω_(s) furthersimplifications are possible,

$\begin{matrix}{i_{1} = {\frac{1}{2}{{{Re}\left\lbrack {\left( {\overset{\_}{s}}_{N} \right)^{*}{\overset{\_}{i}}_{2}} \right\rbrack}.}}} & (16)\end{matrix}$

In (16), s _(N) and ī₂ exist as phasors at the fundamental frequencyω_(s), while i₁ exists as a phasor at zero frequency, written here as aconstant time domain quantity for simplicity.

Equation (11) can also be simplified under the assumption that s_(N) andv₂ both have zero average value. Beginning with the definition of thetruncated Fourier series for v₂ from (13) with N=1,

$\begin{matrix}\begin{matrix}{{v_{2}(t)} = {\overset{+ 1}{\sum\limits_{n = {- 1}}}{{{\hat{v}}_{2}\lbrack n\;\rbrack}{\mathbb{e}}^{{+ j}\;\omega\;{snt}}}}} \\{= {{{{\hat{v}}_{1}\lbrack 0\rbrack}\left( {{{{\hat{s}}_{N}\left\lbrack {+ 1} \right\rbrack}{\mathbb{e}}^{{+ {j\omega}}\;{st}}} + {{{\hat{s}}_{N}\left\lbrack {- 1} \right\rbrack}{\mathbb{e}}^{{- {j\omega}}\;{st}}}} \right)} + {\frac{1}{2\;}{{Re}\left\lbrack {\left( {\overset{\_}{s}}_{N} \right)^{*}{\overset{\_}{v}}_{1}} \right\rbrack}}}} \\{= {{{{\hat{v}}_{1}\lbrack 0\rbrack}{{Re}\left\lbrack {{\overset{\_}{s}}_{N}{\mathbb{e}}^{{+ {j\omega}_{s}}t}} \right\rbrack}} + {\frac{1}{2}{{{Re}\left\lbrack {\left( {\overset{\_}{s}}_{N} \right)^{*}{\overset{\_}{v}}_{1}} \right\rbrack}.}}}}\end{matrix} & (17)\end{matrix}$

For systems in which the input voltage is assumed constant, the phasor v₁ in the fundamental frequency is zero. This results in

$\begin{matrix}\begin{matrix}{{v_{2}(t)} = {v_{1}{{Re}\left\lbrack {{\overset{\_}{s}}_{N}{\mathbb{e}}^{{+ {j\omega}_{s}}t}} \right\rbrack}}} \\{{= {v_{1}{s_{N}(t)}}}\;}\end{matrix} & (18) \\{{\therefore{\overset{\_}{v}}_{2}} = {v_{1}{{\overset{\_}{s}}_{N}.}}} & \;\end{matrix}$

FIG. 7 is a phasor transformer model of a full bridge switch networkwith associated left-to-right voltage conversion and right-to-leftcurrent conversion ratios. Together (16) and (18) fully describe theequivalent transformer in a system which is approximated by limitingfrequency content to lower frequencies than the fundamental harmonic andwith constant voltage v₁. As all quantities are phasors this equivalentcircuit model is defined as the “phasor transformer.” These results aresummarized below and in FIG. 7.

$\begin{matrix}{{i_{1} = {\frac{1}{2}{{Re}\left\lbrack {\left( {\overset{\_}{s}}_{N} \right)^{*}{\overset{\_}{i}}_{2}} \right\rbrack}}},} & (19) \\{{\overset{\_}{v}}_{2} = {v_{1}{{\overset{\_}{s}}_{N}.}}} & (20)\end{matrix}$

Using these equations and the equivalent circuit for the phasortransformer as a model for switch networks greatly simplifies theanalysis of the DABSRC. Equations (20) and (19) are all that is neededfor steady state analysis, while small signal models follow by extensionand are discusses below.

III.2 Steady State Analysis

Steady state analysis of the DABSRC focuses on enabling three tasks.First, it must be possible to design a converter whose output meetsbasic design specifications. Once this is accomplished maintainingreasonable component stresses becomes the focus. Finally, once aconverter with acceptable output capabilities and reasonable componentstresses has been designed the steady state control space must beinvestigated in order to achieve the highest steady state efficiency. Inactuality these three areas are closely coupled with each other suchthat none may be individually optimized. As is generally the case insuch situations, an iterative design methodology is applied. Therigorous three parameter constrained optimization problem possible inthis situation is left to future work.

Although the design process for the DABSRC is of necessity iterative,logically the steps involved are well organized. First the tank currentsand voltages are calculated, leading to expressions for RMS voltage andcurrents as well as component stress approximations. These expressionsare then used to calculate power flow at both input and output for threeangle control of the DABSRC. Finally the resonant tank values andswitching components are selected based on the previous analysis.

FIG. 8 is a phasor model of the Dual Active Bridge Series ResonantConverter. The phasor transformer model replaces both active switchnetworks. Substitution of the phasor transformer derived above into theDABSRC results in the equivalent circuit of FIG. 8. The angle defined asφ_(A) in previous sections for the primary side phasor transformer isfixed at zero, while the other three available phasor transformer anglesrelate directly to the three angles used for power flow control in theDABSRC. The isolation transformer of FIG. 2B has been combined with thesecondary side transformer, with the resulting two phasor turns ratios,

$\begin{matrix}\begin{matrix}{{{\overset{\_}{s}}_{AB}\left( \varphi_{AB} \right)} = {\frac{2}{j\pi}\left( {1 - {\mathbb{e}}^{- {j\varphi}_{AB}}} \right)}} \\{= {\frac{4}{\pi}{\sin\left( \frac{\varphi_{AB}}{2} \right)}{\mathbb{e}}^{{- j}\;\frac{\varphi_{AB}}{2}}}} \\{{= {S_{AB}{\mathbb{e}}^{{- j}\;\frac{\varphi_{AB}}{2}}}},}\end{matrix} & (21) \\\begin{matrix}{{{\overset{\_}{s}}_{D\; C}\left( {\varphi_{AD},\varphi_{D\; C}} \right)} = {\frac{2{\mathbb{e}}^{- {j{({\varphi_{D\; C} + \varphi_{AD}})}}}}{j\; n\;\pi}\left( {{\mathbb{e}}^{j\;\varphi_{D\; C}} - 1} \right)}} \\{= {\frac{4}{n\;\pi}{\sin\left( \frac{\varphi_{D\; C}}{2} \right)}{\mathbb{e}}^{- {j{({\varphi_{A\; D} + \frac{\varphi_{D\; C}}{2}})}}}}} \\{= {S_{D\; C}{{\mathbb{e}}^{- {j{({\varphi_{{AD}\;} + \frac{\varphi_{D\; C}}{2}})}}}.}}}\end{matrix} & (22)\end{matrix}$for primary and secondary switch networks, respectively. Equations (21)and (22) result from application of (15) onto (7) with N=1. For theremainder of this paper, n is assumed to equal one in order to simplifyexamples and derivations.

Assuming a constant input and output voltage, the applied tank voltagesv _(AB) and v _(DC) in FIG. 8 are found with (20),

$\begin{matrix}\begin{matrix}{{{\overset{\_}{v}}_{AB}\left( \varphi_{AB} \right)} = {v_{I\; N}{{\overset{\_}{s}}_{AB}\left( \varphi_{AB} \right)}}} \\{= {v_{I\; N}S_{AB}{\mathbb{e}}^{j\; - \frac{\varphi_{AB}}{2}}}} \\{{= {v_{AB}{\mathbb{e}}^{j\;\varphi_{AB}}}},}\end{matrix} & (23) \\\begin{matrix}{{{\overset{\_}{v}}_{D\; C}\left( {\varphi_{AD},\varphi_{D\; C}} \right)} = {v_{OUT}{{\overset{\_}{s}}_{D\; C}\left( {\varphi_{AD},\varphi_{D\; C}} \right)}}} \\{= {v_{OUT}S_{D\; C}{\mathbb{e}}^{- {j{({\varphi_{AD} + \frac{\varphi_{D\; C}}{2}})}}}}} \\{= {V_{D\; C}{{\mathbb{e}}^{{j\varphi}_{VDC}}.}}}\end{matrix} & (24)\end{matrix}$

Applying these voltages across the complex tank impedance with theinclusion of series resistor R_(r) to model tank losses

$\begin{matrix}{{{z_{T}\left( \omega_{s} \right)} = {{R_{r} + {j\left( {{\omega_{s}L_{r}} - \frac{1}{\omega_{s}C_{r}}} \right)}} = {R_{r} + {j\left( \frac{Z_{O}}{H_{o}\left( \omega_{s} \right)} \right)}}}}{{H_{O}\left( \omega_{s} \right)} = \frac{\left( {\omega_{o}/\omega_{s}} \right)}{1 - \left( {\omega_{o}/\omega_{s}} \right)^{2}}}{Z_{O} = \sqrt{\frac{L_{r}}{C_{r}}}}{{\omega_{o} = \frac{1}{\sqrt{L_{r}C_{r}}}},}} & (25)\end{matrix}$evaluated at the switching frequency co, defines the steady state phasortank current,

$\begin{matrix}{{{\overset{\_}{i}}_{T} = {\frac{{\overset{\_}{v}}_{AB} - {\overset{\_}{v}}_{D\; C}}{z_{T}\left( \omega_{s} \right)} = {K_{T}{\mathbb{e}}^{j\;\varphi_{T}}}}},{K_{T} = {\frac{v_{I\; N}\sqrt{S_{AB}^{2} + {M^{2}S_{D\; C}^{2}} - {2{MS}_{AB}S_{D\; C}{\cos\left( {\varphi_{VAB} - \varphi_{VDC}} \right)}}}}{{z_{T}\left( \omega_{s} \right)}}.}}} & (26)\end{matrix}$

Conversion ratio M is defined as output voltage v_(OUT) over inputvoltage v_(IN) times the transformer turns ratio n.

Using (26), the RMS tank current can be found as

$\begin{matrix}{{{{RMS}\left\lbrack I_{T} \right\rbrack} = \frac{K_{T}}{\sqrt{2}}},} & (27)\end{matrix}$with the theoretical maximum RMS tank current

$\begin{matrix}{{\underset{\varphi_{AB},\varphi_{AD},\varphi_{D\; C}}{{MAX}\left\lbrack {{RMS}\left\lbrack I_{T} \right\rbrack} \right\rbrack} = {\frac{2\sqrt{2}}{\pi}\frac{v_{IN}}{{z_{T}\left( \omega_{s} \right)}}\left( {1 + M} \right)}},} & (28)\end{matrix}$when φ_(AB)=φ_(AD)=φ_(DC)=π.

The peak resonant capacitor voltage can be found as the scaled magnitudeof the time integral of ī_(T). The actual value of this maximum voltagedepends on whether a split capacitor is used or not, but is easilyderived in either case. For a single capacitor on the secondary side ofthe tank isolation transformer, this voltage is found to be equal to

$\begin{matrix}{\underset{\varphi_{AB},\varphi_{AD},\varphi_{D\; C}}{{MAX}\left\lbrack V_{CS} \right\rbrack} = {\frac{4v_{IN}}{n\;\pi\;\omega_{s}C_{r}{{z_{T}\left( \omega_{s} \right)}}}{\left( {1 + M} \right).}}} & (29)\end{matrix}$

When a primary side resonant capacitor is used, the resulting in amaximum capacitor voltage is found to be n times (29). For a splitcapacitor system such as the one shown in FIG. 2B the maximum capacitorvoltage is simply equal to ½ of the value shown above for the secondaryside capacitor, and n times this value for the primary side capacitor.

Equations (28) and (29) relate to the maximum theoretical values acrossall possible control angles. When control angles are constrained tofollow a set path in the three dimensional control space, these actualmaximum values encountered may be far smaller.

Input and output currents for the DABSRC are found by applying (19)directly to the converter model in FIG. 8,

$\begin{matrix}{{i_{IN} = {\frac{K_{T}S_{AB}}{2}{\cos\left( {\varphi_{T} - \varphi_{VAB}} \right)}}},} & (30) \\{i_{OUT} = {\frac{K_{T}S_{D\; C}}{2}{{\cos\left( {\varphi_{T} - \varphi_{VDC}} \right)}.}}} & (31)\end{matrix}$

Multiplying by the appropriate voltage results in expressions for theinput and output powers with respect to the three control angles used.Doing so results in a simple expression for the maximum possible outputpower assuming an ideal tank,

$\begin{matrix}{{{\underset{\varphi_{AB},\varphi_{AD},\varphi_{D\; C}}{{MAX}\left\lbrack P_{o} \right\rbrack}}_{R_{r} = 0} = {P_{o}^{M\;{ax}} = {\frac{8M}{\pi^{2}}\frac{\left( v_{IN} \right)^{2}}{{{z_{T}(\omega)}}_{R_{r} = 0}}}}},} & (32)\end{matrix}$achieved at φ_(AB)=φ_(DC)=π and φ_(AD)=π/2. Determining the maximumoutput power with a non-zero tank resistance is best done with anumerical optimization, as the resulting shift in tank current phaseresults in slightly modified control angles needed to achieve themaximum available power output.

Equations (26)-(32) along with the associated phase and magnitude forphasor quantities fully define all steady state signals of the DABSRCaccording to a fundamental approximation. These results allow a powerstage to be intelligently designed according to project specifications.

Based on steady state analysis of the DABSRC, a V_(IN)=500 V converteris designed with a nominal conversion ratio of M=1. A switchingfrequency of f_(s)=100 kHz is chosen. Because the ratio of RMS tankcurrent to delivered output current is lowest at a unity conversionratio, a transformer turns ratio of n=1 is chosen. A nominal outputpower of P_(o) ^(MAX)=1 kW is desired, helping to force the selection oftank parameters using (32). This output power must be maintained down toa conversion ratio of M=0.4, while at M=1 a pulsed power of P_(o)^(BURST)=2 kW must be delivered. These constraints allow (32) to besolved for the magnitude of the tank impedance necessary at theswitching frequency,

$\begin{matrix}{{{{z_{T}\left( \omega_{s} \right)}}_{R_{r} = 0}} = {\frac{8M}{\pi^{2}}{\frac{\left( v_{IN} \right)^{2}}{P_{o}^{M\;{ax}}}.}}} & (33)\end{matrix}$

An additional constraint on the tank impedance is set by requiring themaximum resonant capacitor voltages to remain below 400 V for the splittank capacitor design seen in FIG. 2B. This maximum capacitor voltageconstraint leads to a necessary ratio between the resonant tankfrequency ω_(o) defined in (25) and the switching frequency ω_(s) of

$\begin{matrix}{\frac{\omega_{o}}{\omega_{s}} = {0.61.}} & (34)\end{matrix}$

A combination of these constraints can now be used to determine thespecific tank parameters, resulting in a resonant tank inductance ofL_(r)=200 μH and a total resonant capacitance of C_(r)=34 nF. C_(r) isimplemented as a split capacitor using two capacitors of twice thenominal value located on either side of the isolation transformer. Thisis done in order to ensure that zero average current is maintained inboth the primary and secondary windings of the tank transformer withoutthe need for average current control. This simple approach for maintainzero average current has the drawback of increasing the tank volume. Inorder to remove this issue, it may be possible to use a single capacitordue to the inherent volt-second balancing achieved in some resonantconverters, although this extension is left for future revisions. L_(r)is additionally split in order to increase symmetry for the inputbridges.

III.3 Small Signal Analysis of the DABSRC

Small signal analysis of the DABSRC begins with defining a small signalmodel of the phasor transformer. This derivation is done assuming thatan ideal voltage source is used as an input on the primary side with anarbitrary impedance loading the secondary side of the transformer model.Perturbations are applied to control angles only with the input voltagesof each equivalent transformer assumed to be constant. The primary sideequivalent transformer input voltage is defined as the constant DABSRCinput voltage, while the secondary side equivalent transformer inputvoltage is defined as the constant DABSRC output voltage. By perturbingeach of the control angles, small signal voltage perturbations on theapplied AC tank voltage is predicted. Once a small signal model for thephasor transformer has been derived, it is inserted into a linearizedsmall signal model of the full DABSRC with small signal phasor tankimpedance. This converter model is used to derive small signal tankcurrents, and used in conjunction with the large signal model of theconverter derived in Section III.2 above in order to derive small signalinput and output currents.

Beginning with the non-zero terms of (6), the first two terms of a twovariable Taylor series expansion around a steady state phase vectorV_(Φ)={Φ_(A),Φ_(AB)} can be used as a linear approximation of theequivalent transformer output voltage,

$\begin{matrix}{{{{{{{{{{\hat{v}}_{2}\lbrack n\rbrack} \approx {{\hat{v}}_{2}\lbrack n\rbrack}}}_{V_{\Phi}} + {{\overset{\sim}{\varphi}}_{a}\frac{\partial{{\hat{v}}_{2}\lbrack n\rbrack}}{\partial\varphi_{A}}}}}_{V_{\Phi}} + {{\overset{\sim}{\varphi}}_{ab}\frac{\partial{{\hat{v}}_{2}\lbrack n\rbrack}}{\partial\varphi_{AB}}}}}_{V_{\Phi}} \approx {{{\hat{V}}_{2}\lbrack n\rbrack} + {{\overset{\sim}{\varphi}}_{a}{{\hat{v}}_{2}^{A}\lbrack n\rbrack}} + {{\overset{\sim}{\varphi}}_{ab}{{\hat{v}}_{2}^{AB}\lbrack n\rbrack}}}},{\approx {{{\hat{V}}_{2}\lbrack n\rbrack} + {{\overset{\hat{\sim}}{v}}_{2}\lbrack n\rbrack}}},} & (35) \\{\mspace{20mu}{{{{\hat{v}}_{2}^{A}\lbrack n\rbrack} = {{- \frac{v_{1}{\mathbb{e}}^{{- j}\; n\;\Phi_{A}}}{\pi}}\left( {1 - {\mathbb{e}}^{{- j}\; n\;\Phi_{AB}}} \right)}},}} & (36) \\{\mspace{20mu}{{{\hat{v}}_{2}^{AB}\lbrack n\rbrack} = {\frac{v_{1}}{\pi}{{\mathbb{e}}^{{- j}\;{n{({\Phi_{A} + \Phi_{AB}})}}}.}}}} & (37)\end{matrix}$

Equations (36) and (37) represent the linear approximation of the effectof φ_(A) and φ_(AB) perturbations on v₂ and can be represented as twocomplex voltage sources in series on the secondary side of theequivalent transformer.

Due to the small signal voltage sources from (35), current i₂ will reactdependent on the relation between v₂ and i₂ in circuit. Regardless ofthe specific relation, current i₂ will react with magnitude and phaseperturbations,î ₂ [n]=(K ₂ [n]+{tilde over (k)} ₂ [n])e ^(j(Φ) ²^([n]+{tilde over (Φ)}) ² ^([n])).  (38)

Applying the transformer relation from (10) to (38) results in anon-linear input current in terms of the magnitude and phase of i₂, aswell as the phase control angles φ_(A) and φ_(AB). Using a four variableTaylor series expansion this expression can be linearized as a sum ofsmall signal sources,

$\begin{matrix}{{{\hat{i}}_{1}\lbrack n\rbrack} = {{{{\hat{s}}_{N}\lbrack n\rbrack}*{{\hat{i}}_{2}\lbrack n\rbrack}} \approx {{I_{1}\lbrack n\rbrack} + {{\overset{\sim}{\varphi}}_{a}{{\hat{i}}_{1}^{A}\lbrack n\rbrack}} + {{\overset{\sim}{\varphi}}_{ab}{{\hat{i}}_{1}^{AB}\lbrack n\rbrack}} + {{\overset{\sim}{k}}_{2}{{\hat{i}}_{1}^{k}\lbrack n\rbrack}} + {{\overset{\sim}{\varphi}}_{2}{{\hat{i}}_{1}^{\varphi}\lbrack n\rbrack}}} \approx {{{\hat{I}}_{1}\lbrack n\rbrack} + {{{\overset{\hat{\sim}}{i}}_{1}\lbrack n\rbrack}.}}}} & (39)\end{matrix}$

The difficulty in directly applying (39) results from the need to expandthe small signal tank magnitude and phase in terms of the two controlangle variables. Because this expansion includes terms dependent on theunknown v₂−i₂ relation, (39) is left as is for the general form of theequivalent transformer small signal model. An example of expanding (39)once the tank impedance is known is given later in this section for theDABSRC.

FIG. 9 is a general small signal model of a full bridge switch networkrepresented as an equivalent transformer. Equations (38) and (39) arerepresented in circuit form in FIG. 9 and presented as the general smallsignal model of the equivalent transformer.

Phasor representation of inductors and capacitors as small signalelements has been previously dealt with. The results, duplicated herefor clarity, show that capacitors and inductors require the addition ofan imaginary resistance,

$\begin{matrix}{{R_{C} = \frac{1}{j\;\omega_{s}C_{r}}},} & (40) \\{{R_{L} = {j\;\omega_{s}L_{r}}},} & (41)\end{matrix}$where R_(C) is added in parallel with C_(r) and R_(L) added in serieswith L_(r) as seen in FIG. 10. FIG. 10 is a small signal equivalent tankimpedance for the DABSRC. Imaginary resistors R_(L) and R_(C) are addedto reactive elements, while R_(r) models tank losses. These imaginaryresistances represent the linearized effect of variations in switchingfrequency on the tank impedances. Although switching frequency is notvaried in this work, the effect of phase shift variations results in anequivalent expression for imaginary resistance due to the relationshipbetween switching frequency and phase shift. In FIG. 10 a seriesresistance is added in order to represent tank losses. The resultingsmall signal tank impedance takes the form

$\begin{matrix}{{{z_{t}\left( {\omega_{s} - {j\; s}} \right)} = {R_{r} + {L_{r}\left( {{j\omega}_{s} + s} \right)} + \frac{1}{\left( {{j\;\omega_{s}} + s} \right)C_{r}}}},} & (42)\end{matrix}$

This expression is equivalent to evaluating (25) at (ω_(s)−js).Resistors, current sources, and voltage sources retain their form, withvoltage and current source values converted into their phasorequivalents. To complete the small signal model of the DABSRC, only thesmall signal representation of the phasor transformer need be applied.

Rephrasing (36) and (37) in terms of the converter control angles andapplying (15) in order to achieve phasor quantities results in threesmall signal phasor sources. The single control angle applied to theprimary switch network results in a single small signal source resultingfrom a sum of (36) and (37) evaluated with n=+1,

$\begin{matrix}{{{\overset{\_}{v}}_{ab}^{AB}{\overset{\sim}{\varphi}}_{ab}} = {{\overset{\sim}{\varphi}}_{ab}\frac{2V_{IN}}{\pi}{{\mathbb{e}}^{{- j}\;\Phi_{AB}}.}}} & (43)\end{matrix}$

The secondary side switch network results in a pair of small signalsources, after collecting terms for each of the two control angles,

$\begin{matrix}{{{{\overset{\_}{v}}_{d\; c}^{AD}{\overset{\sim}{\varphi}}_{ad}} = {{- {\overset{\sim}{\varphi}}_{ad}}\frac{j\; 2{MV}_{I\; N}}{\pi}{\sin\left( \frac{\Phi_{D\; C}}{2} \right)}{\mathbb{e}}^{j{({\Phi_{AD} + \frac{\Phi_{D\; C}}{2}})}}}},} & (44) \\{{{\overset{\_}{v}}_{d\; c}^{D\; C}{\overset{\sim}{\varphi}}_{d\; c}} = {{- {\overset{\sim}{\varphi}}_{d\; c}}\frac{2{MV}_{IN}}{\pi}{{\mathbb{e}}^{- {j{({\Phi_{AD} + \Phi_{D\; C}})}}}.}}} & (45)\end{matrix}$

The small signal tank current is computed as a function of the threesmall signal voltage sources (43)-(45) applied across the tank impedance(42) and can be split into real and imaginary portions,

$\begin{matrix}\begin{matrix}{{{\overset{\overset{\sim}{\_}}{i}}_{t} = {\frac{1}{z_{T}\left( {\omega_{s} - {j\; s}} \right)}\left( {{{\overset{\_}{v}}_{ab}^{AB}{\overset{\sim}{\varphi}}_{ab}} + {{\overset{\_}{v}}_{d\; c}^{AD}{\overset{\sim}{\varphi}}_{ad}} + {{\overset{\_}{v}}_{d\; c}^{D\; C}{\overset{\sim}{\varphi}}_{d\; c}}} \right)}},} \\{= {{\overset{\sim}{i}}_{tx} + {{j\left( {\overset{\sim}{i}}_{ty} \right)}.}}}\end{matrix} & (46)\end{matrix}$

To obtain magnitude and phase envelopes for the tank current of theDABSRC, the complex phasor relation in (46) is split into two realfunctions which separately relate magnitude and phase to each of thethree control angle perturbations. This has previously been done for themagnitude envelope of a phasor signal, but not for the phase envelope ofa phasor signal. Both equations are derived by linearizing the equationsfor the magnitude and phase of a complex number in rectangular form witha first order Taylor series expansion. For some phasor g with steadystate complex value G=G_(X)+jG_(Y) and small signal value g={tilde over(g)}_(x)+j{tilde over (g)}_(y) this results in

$\begin{matrix}{{\overset{\_}{g}} \approx \frac{{{\overset{\sim}{g}}_{x}G_{X}} + {{\overset{\sim}{g}}_{y}G_{Y}}}{G}} & (47) \\{{\angle\;\overset{\_}{g}} \approx {\frac{{{\overset{\sim}{g}}_{y}G_{X}} - {{\overset{\sim}{g}}_{x}G_{Y}}}{{G}^{2}}.}} & (48)\end{matrix}$

Applying (47) and (48) to (46) results in expressions for the linearizedeffect of each of the three control angles on both the magnitude and thephase of the small signal tank current phasor,

$\begin{matrix}\begin{matrix}{{{\overset{\overset{\sim}{\_}}{i}}_{t}} = {{{\overset{\sim}{i}}_{tx}{\cos\left( \Phi_{T} \right)}} + {{\overset{\sim}{i}}_{ty}{\sin\left( \Phi_{T} \right)}}}} \\{= {{k_{t}^{AB}{\overset{\sim}{\varphi}}_{ab}} + {k_{t}^{AD}{\overset{\sim}{\varphi}}_{ad}} + {k_{t}^{D\; C}{\overset{\sim}{\varphi}}_{d\; c}}}} \\{{= {\overset{\sim}{k}}_{t}},}\end{matrix} & (49) \\\begin{matrix}{{\angle{\overset{\overset{\sim}{\_}}{i}}_{t}} = \frac{{{\overset{\sim}{i}}_{ty}{\cos\left( \Phi_{T} \right)}} + {{\overset{\sim}{i}}_{tx}{\sin\left( \Phi_{T} \right)}}}{K_{T}}} \\{= {{k_{t}^{AB}{\overset{\sim}{\varphi}}_{ab}} + {k_{t}^{AD}{\overset{\sim}{\varphi}}_{ad}} + {k_{t}^{D\; C}{\overset{\sim}{\varphi}}_{d\; c}}}} \\{= {{\overset{\sim}{\varphi}}_{t}.}}\end{matrix} & (50)\end{matrix}$

The order of the transfer functions in (49)-(50) depends directly on thesmall signal tank impedance. Due to the form of (47) and (48), the threetransfer functions in (49) have equal order to the number of zeroes inthe small signal tank impedance, while the three transfer functions in(50) have a highest possible order of the number of zeroes in the smallsignal tank impedance squared.

To derive linear models for the input and output currents relation toeach of the three control angles requires revisiting a large signalmodel of the DABSRC. Linearizing the large signal input and outputcurrents in (30) and (31) results in expressions for small signalperturbation in terms of the tank current components found in (49) and(50). This is done by treating the tank current and phase as quantitieswith no dependence on control angle, and then using the chain rule toexpand the result in terms of the dependence on each of the threecontrol angles. After substituting the correct quantities, the desiredresults are achieved.

Beginning with the large signal input current of the DABSRC derivedpreviously,

$\begin{matrix}{{i_{IN} = {\frac{K_{T}S_{AB}}{2}{\cos\left( {\varphi_{T} - \varphi_{VAB}} \right)}}},} & (51)\end{matrix}$partial derivatives are taken with respect to both the tank currentmagnitude K_(T) and tank current phase φ_(T), as well as with respect tothe three control angles,

$\begin{matrix}{{\overset{\sim}{i}}_{IN} = {{{\overset{\sim}{k}}_{t}\frac{\partial i_{IN}}{\partial k_{T}}} + {{\overset{\sim}{\varphi}}_{t}\frac{\partial i_{IN}}{\partial\varphi_{T}}} + {{\overset{\sim}{\varphi}}_{a\; b}\frac{\partial i_{IN}}{\partial\varphi_{AB}}} + {{\overset{\sim}{\varphi}}_{ad}\frac{\partial i_{IN}}{\partial\varphi_{AD}}} + {{\overset{\sim}{\varphi}}_{d\; c}{\frac{\partial i_{IN}}{\partial\varphi_{D\; C}}.}}}} & (52)\end{matrix}$

For the input current, two of these terms are zero as there is no directdependence on either φ_(AD) or φ_(DC). The dependence of k_(T) and φ_(T)on the three control angles is dealt with by using the chain rule toexpand the first two terms of (52),

$\begin{matrix}{{{\overset{\sim}{k}}_{t}\frac{\partial i_{IN}}{\partial k_{T\;}}} = {{\overset{\sim}{k}}_{t}\left( {{\frac{\partial i_{IN}}{\partial k_{T}}\frac{\partial k_{T}}{\partial\varphi_{AB}}} + {\frac{\partial i_{IN}}{\partial k_{T}}\frac{\partial k_{T}}{\partial\varphi_{AD}}} + {\frac{\partial i_{IN}}{\partial k_{T}}\frac{\partial k_{T}}{\partial\varphi_{D\; C}}}} \right)}} & (53) \\{{{\overset{\sim}{\varphi}}_{t}\frac{\partial i_{IN}}{\partial\varphi_{T\;}}} = {{{\overset{\sim}{\varphi}}_{t}\left( {{\frac{\partial i_{IN}}{\partial\varphi_{T}}\frac{\partial\varphi_{T}}{\partial\varphi_{AB}}} + {\frac{\partial i_{IN}}{\partial\varphi_{T}}\frac{\partial\varphi_{T}}{\partial\varphi_{AD}}} + {\frac{\partial i_{IN}}{\partial\varphi_{T}}\frac{\partial\varphi_{T}}{\partial\varphi_{D\; C}}}} \right)}.}} & (54)\end{matrix}$

Each of the six partial derivatives in (53) and (54) with respect to thethree control angles have been previously derived in (49) for the tankcurrent magnitude and in (50) for the tank current phase. Substitutingthe results into (53) and (54) and canceling terms results inexpressions for the partial derivative of the input current with respectto both tank current and tank phase perturbations which are dependent ononly the three control angles perturbations,

$\begin{matrix}{{{{\overset{\sim}{k}}_{t}\frac{\partial i_{IN}}{\partial k_{T\;}}} = \left( {{\frac{\partial i_{IN}}{\partial k_{T}}k_{t}^{AB}{\overset{\sim}{\varphi}}_{ab}} + {\frac{\partial i_{IN}}{\partial k_{T}}k_{t}^{AD}{\overset{\sim}{\varphi}}_{ad}} + {\frac{\partial i_{IN}}{\partial k_{T}}k_{t}^{D\; C}{\overset{\sim}{\varphi}}_{d\; c}}} \right)},} & (55) \\{{{\overset{\sim}{\varphi}}_{t}\frac{\partial i_{IN}}{\partial\varphi_{T\;}}} = {\left( {{\frac{\partial i_{IN}}{\partial\varphi_{T}}\varphi_{t}^{AB}{\overset{\sim}{\varphi}}_{ab}} + {\frac{\partial i_{IN}}{\partial\varphi_{T}}\varphi_{t}^{AD}{\overset{\sim}{\varphi}}_{ab}} + {\frac{\partial i_{IN}}{\partial\varphi_{T}}\varphi_{t}^{D\; C}{\overset{\sim}{\varphi}}_{d\; c}}} \right).}} & (56)\end{matrix}$

Inserting (55) and (56) into (52) results in the desired equation forthe small signal input current. These equations can now be rearrangedinto three separate terms, each relating a single control angle withsmall signal input current perturbations,

$\begin{matrix}{{{\overset{\sim}{i}}_{IN} = {{{\overset{\sim}{\varphi}}_{ab}i_{IN}^{AB}} + {{\overset{\sim}{\varphi}}_{ad}i_{IN}^{AD}} + {{\overset{\sim}{\varphi}}_{d\; c}i_{I\; N}^{D\; C}}}},} & (57) \\{{{i_{IN}^{AB}(s)} = \left( {{k_{t}^{AB}\frac{\partial i_{IN}}{\partial k_{T}}} + {\varphi_{t}^{AB}\frac{\partial i_{IN}}{\partial\varphi_{T}}} + \frac{\partial i_{IN}}{\partial\varphi_{AB}}} \right)},} & (58) \\{{{i_{IN}^{AD}(s)} = \left( {{k_{t}^{AD}\frac{\partial i_{IN}}{\partial k_{T}}} + {\varphi_{t}^{AD}\frac{\partial i_{IN}}{\partial\varphi_{T}}}} \right)},} & (59) \\{{i_{IN}^{D\; C}(s)} = {\left( {{k_{t}^{D\; C}\frac{\partial i_{IN}}{\partial k_{T}}} + {\varphi_{t}^{D\; C}\frac{\partial i_{IN}}{\partial\varphi_{T}}}} \right).}} & (60)\end{matrix}$

In (58)-(60), each of the partial derivatives is a gain term dependenton steady state operating point, while each of the multiplying terms isa transfer function as found previously.

Solving for the small signal output current follows the same process,beginning with the large signal output current,

$\begin{matrix}{i_{OUT} = {\frac{K_{T}S_{D\; C}}{2}{{\cos\left( {\varphi_{T} - \varphi_{VDC}} \right)}.}}} & (61)\end{matrix}$

Taking partial derivatives with respect to each of the three controlangles as well as the tank current magnitude and phase results in a sumof six quantities just as before,

$\begin{matrix}{{{\overset{\sim}{i}}_{OUT} = {{{\overset{\sim}{k}}_{t}\frac{\partial i_{OUT}}{\partial k_{T}}} + {{\overset{\sim}{\varphi}}_{t}\frac{\partial i_{OUT}}{\partial\varphi_{T}}} + {{\overset{\sim}{\varphi}}_{ab}\frac{\partial i_{OUT}}{\partial\varphi_{AB}}} + {{\overset{\sim}{\varphi}}_{ad}\frac{\partial i_{OUT}}{\partial\varphi_{AD}}} + {{\overset{\sim}{\varphi}}_{D\; C}\frac{\partial i_{OUT}}{\partial\varphi_{D\; C}}}}},} & (62)\end{matrix}$with the only difference being that the output current has a directdependence on both φ_(AD) and φ_(DC), with no direct dependence onφ_(AB). The derivation proceeds from (62) just as it did for the inputcurrent, resulting in three terms which each relate a single controlangle to small signal output current,

$\begin{matrix}{{{\overset{\sim}{i}}_{OUT} = {{{\overset{\sim}{\varphi}}_{ab}i_{OUT}^{AB}} + {{\overset{\sim}{\varphi}}_{ad}i_{OUT}^{AD}} + {{\overset{\sim}{\varphi}}_{d\; c}i_{OUT}^{D\; C}}}},} & (63) \\{{{i_{OUT}^{AB}(s)} = \left( {{k_{t}^{AB}\frac{\partial i_{OUT}}{\partial k_{T}}} + {\varphi_{t}^{AB}\frac{\partial i_{OUT}}{\partial\varphi_{T}}}} \right)},} & (64) \\{{{i_{OUT}^{AD}(s)} = \left( {{k_{t}^{AD}\frac{\partial i_{OUT}}{\partial k_{T}}} + {\varphi_{t}^{AD}\frac{\partial i_{OUT}}{\partial\varphi_{T}}} + \frac{\partial i_{OUT}}{\partial\varphi_{AD}}} \right)},} & (65) \\{{i_{OUT}^{D\; C}(s)} = {\left( {{k_{t}^{D\; C}\frac{\partial i_{OUT}}{\partial k_{T}}} + {\varphi_{t}^{D\; C}\frac{\partial i_{OUT}}{\partial\varphi_{T}}} + \frac{\partial i_{OUT}}{\partial\varphi_{D\; C}}} \right).}} & (66)\end{matrix}$

The desired results for both input and output current small signalmodels are found in (57) and (63). The transfer functions seen in theseequations have orders dependent on the tank current transfer functionsin (49) and (50). Each of these equations provides a linear relationbetween control action from any of three control inputs and either inputor output current. The constants used in each of these equations aresummarized in Table 1.

TABLE 1 Small Signal Current Constants Small Signal Input and OutputCurrent Constants $\frac{\partial i_{IN}}{\partial k_{T}}$$\frac{1}{\pi}\left( {{\sin\left( {\Phi_{AB} + \Phi_{T}} \right)} - {\sin\left( \Phi_{T} \right)}} \right)$$\frac{\partial i_{IN}}{\partial\varphi_{T}}$$\frac{K_{T}}{\pi}\left( {{\cos\left( {\Phi_{AB} + \Phi_{T}} \right)} - {\cos\left( \Phi_{T} \right)}} \right)$$\frac{\partial i_{IN}}{\partial\varphi_{AB}}$$\frac{K_{T}}{\pi}{\cos\left( {\Phi_{AB} + \Phi_{T}} \right)}$$\frac{\partial i_{OUT}}{\partial k_{T}}$$\frac{1}{\pi}\left( {{\sin\left( {\Phi_{AD} + \Phi_{DC} + \Phi_{T}} \right)} - {\sin\left( {\Phi_{AD} + \Phi_{T}} \right)}} \right)$$\frac{\partial i_{OUT}}{\partial\varphi_{T}}$$\frac{K_{T}}{\pi}\left( {{\cos\left( {\Phi_{AD} + \Phi_{DC} + \Phi_{T}} \right)} - {\cos\left( {\Phi_{AD} + \Phi_{T}} \right)}} \right)$$\frac{\partial i_{OUT}}{\partial\varphi_{AD}}$$\frac{K_{T}}{\pi}\left( {{\cos\left( {\Phi_{AD} + \Phi_{DC} + \Phi_{T}} \right)} - {\cos\left( {\Phi_{AD} + \Phi_{T}} \right)}} \right)$$\frac{\partial i_{OUT}}{\partial\varphi_{DC}}$$\frac{K_{T}}{\pi}{\cos\left( {\Phi_{AD} + \Phi_{DC} + \Phi_{T}} \right)}$IV Control of the DABSRC

With the derivation of small signal models relating each of the threecontrol angles to both input and output currents of the DABSRCcompleted, a feedback controller for the converter can be implemented.

Control of the DABSRC begins with determining the optimal set of controlangles for steady state operation in terms of converter efficiency. Thisoptimization can include both RMS tank currents as well as ZVS regionsfor the converter; although the future inclusion of PSM-HB auxiliarycircuitry on all bridges means that an optimization on only RMS tankcurrents is performed. Once this is completed, the small signal modelsdeveloped for the DABSRC are used to determine a feedback controllerusing the control angle trajectories determined decided upon.

Due to the way in which the ZVS circuitry is designed control of thePSM-HB auxiliary legs is dealt with completely separately from controlof the main power stage as shown below with respect to PSM leg ZVSassistance control. This allows a greatly simplified derivation for ahigh bandwidth ZVS control loop.

Finally, once controllers for the DABSRC and its associated ZVScircuitry are derived, the input and output regulated converter isaugmented with both voltage and power control loops. These outputcontrol loops allow for simplified series and parallel connectionbetween converters, and are the last step in designing a controller forthe DABSRC.

IV.1 Operation Along the MCT

For a lossless resonant tank, the steady state output power of theDABSRC assuming P_(OUT) ^(MAX) as seen in (30)

$\begin{matrix}{{P_{OUT} = {P_{OUT}^{MAX}{\sin\left( \frac{\Phi_{AB}}{2} \right)}{\sin\left( \frac{\Phi_{D\; C}}{2} \right)}{\sin\left( {\Phi_{AD} + \frac{\Phi_{D\; C} - \Phi_{AB}}{2}} \right)}}},} & (67)\end{matrix}$is a function of all three control angles, while the maximum outputpower is a function of the converter tank design, operating frequency,and input and output voltages. Normalizing by the maximum output powerthe expression for the normalized output power of the converter,

$\begin{matrix}{\left\langle P_{OUT} \right\rangle_{P_{OUT}^{MAX}} = {\sin\left( \frac{\Phi_{AB}}{2} \right){\sin\left( \frac{\Phi_{D\; C}}{2} \right)}{\sin\left( {\Phi_{AD} + \frac{\Phi_{D\; C} - \Phi_{AB}}{2}} \right)}}} & (68)\end{matrix}$is equal to the expression for the normalized output current of theconverter assuming an ideal voltage source on the output of the DABSRC,

$\begin{matrix}{\left\langle I_{OUT} \right\rangle_{I_{OUT}^{MAX}} = {\sin\left( \frac{\Phi_{AB}}{2} \right){\sin\left( \frac{\Phi_{D\; C}}{2} \right)}{{\sin\left( {\Phi_{AD} + \frac{\Phi_{D\; C} - \Phi_{AB}}{2}} \right)}.}}} & (69)\end{matrix}$

Due to this equivalency, a normalized output command variable,U _(OUT) =

I _(OUT)

=

P _(OUT)

  (70)is defined. With this notation, each desired normalized output U_(OUT)has an associated actual output U_(OUT) which exists between the maximumachievable normalized output +U_(OUT,MAX)=1 and the minimum achievablenormalized output, −U_(OUT,MAX)=−1.

The RMS tank current of the DABSRC is also defined as a function of thethree converter control angles, as seen previously in (27). As the RMStank current is directly related to conduction losses, the optimalselection of steady state converter N control angles is one whichminimizes the RMS tank current while still achieving the desirednormalized output command.

For a given steady state output command the goal is to operate theconverter with the minimum RMS tank current possible. This objective isequivalently expresses by the following constrained minimizationproblem,

$\begin{matrix}{\min\limits_{v_{\varphi} \in C_{s}}{\left\lbrack {{RMS}\left\lbrack I_{T} \right\rbrack} \right\rbrack\text{:}\mspace{14mu}\left\{ {\begin{matrix}{{U_{OUT}\left( v_{\varphi} \right)} = U_{OUT}} \\{{- U_{{OUT},{MAX}}} \leq U_{OUT} \leq {+ U_{{OUT},{MAX}}}}\end{matrix},} \right.}} & (71) \\{{v_{\varphi} = \left\lbrack {\varphi_{AB},\varphi_{AD},\varphi_{D\; C}} \right\rbrack},} & (72) \\{C_{s} = {v_{\varphi}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{{- \pi} \leq \varphi_{AD} \leq {+ \pi}} \\{0 \leq \varphi_{AB} \leq {2\pi}} \\{0 \leq \varphi_{D\; C} \leq {2\pi}}\end{matrix},} \right.}} & (73)\end{matrix}$whose solutions are the minimum current points of U_(OUT); as U_(OUT)varies in the possible range of outputs, the solution describes atrajectory in the control space v_(φ), referred to as the minimumcurrent trajectory (MCT). Using the results from above regarding tankvoltage and currents and steady state power flow with three anglemodulation, (71) can be stated as a system of trigonometric equations,the solution of which can be put in closed form. The form of thesesolutions depends on the conversion ratio M as follows:

When M≦1: The MCT is a 2-D curve lying on the φ_(DC)=π plane. For|U_(OUT)|≧(1−M²)^(1/2) the MCT consists of a single branch in whichφ_(AB)=π while φ_(AD) controls converter output power/current. Thisbranch along which only φ_(AD) varies is denoted as γ₂. For|U_(OUT)|≦(1−M²)^(1/2) the MCT splits into two branches, γ₁, and γ¹⁻, onwhich power/current flow is controlled by both φ_(AD) and φ_(AB).Analytical expressions for the MCT in the M<1 case are

$\begin{matrix}{\gamma_{1 \pm}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = {{\pi \pm \pi} \mp {2{\arcsin\left( \sqrt{M^{2} + \left( U_{OUT} \right)^{2}} \right)}}}} \\{\varphi_{D\; C} = \pi} \\{\varphi_{AD} = {\frac{\varphi_{AB}}{2} + {\arctan\left( \frac{U_{OUT}}{M} \right)} - \frac{\pi}{2}}}\end{matrix},{{{when}\mspace{14mu}{U_{OUT}}} \leq {\sqrt{1 - M^{2}}\gamma_{2}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = {\varphi_{D\; C} = \pi}} \\{\varphi_{AD} = {\arcsin\left( U_{OUT} \right)}}\end{matrix},{{{when}\mspace{14mu}{U_{OUT}}} \geq {\sqrt{1 - M^{2}}.}}} \right.}}} \right.} & (74)\end{matrix}$

When M≧1: The MCT is a 2-D curve lying on the φ_(AB)=π plane. For|U_(OUT)|≧(1−M²)^(1/2) the MCT consists of a single branch in whichφ_(DC)=π while φ_(AD) controls converter output power/current. Thisbranch along which only φ_(AD) varies is denoted as λ₂ and is equivalentto γ₂. For |U_(OUT)|≦(1−M²)^(1/2) the MCT splits into two branches, λ₁₊and λ¹⁻, on which power/current flow is controlled by both φ_(AD) andφ_(DC). Analytical expressions for the MCT in the M>1 case are

$\begin{matrix}{\lambda_{1 \pm}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = \pi} \\{\varphi_{D\; C} = {{\pi \pm \pi} \mp {2{\arcsin\left( \sqrt{\left( \frac{1}{M} \right)^{2} + \left( U_{OUT} \right)^{2}} \right)}}}} \\{\varphi_{AD} = {\frac{- \varphi_{D\; C}}{2} + {\arctan\left( {M \cdot U_{OUT}} \right)} + \frac{\pi}{2}}}\end{matrix},{{{when}\mspace{14mu}{\left\langle U_{OUT} \right\rangle }} \leq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}\lambda_{2}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = {\varphi_{D\; C} = \pi}} \\{\varphi_{AD} = {\arcsin\left( U_{OUT} \right)}}\end{matrix},{{{when}\mspace{14mu}{\left\langle U_{OUT} \right\rangle }} \geq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}.}}} \right.}}} \right.} & (75)\end{matrix}$

For either of the above cases when trajectories λ_(1±) and γ_(1±) areused the bridge with the higher voltage operates with a phase shift notequal to π, while the bridge with the lower voltage operates with aphase shift equal to π. This scheme results in a minimum voltagedifference across the tank, as the high voltage bridge is modulated toreduce the applied voltage-second waveform. Due to the reduceddifference in applied voltages across the tank the peak values of thetank current waveform are reduced, thus reducing the RMS value of thewaveform. Both cases collapse to the same solution at a conversion ratioof M=1. At this conversion ratio single angle modulation of φ_(AD) alonealong either γ₂ or equivalently λ₂ is shown to minimize RMS tankcurrents.

FIG. 11 depicts MCT (solid curve) and normalized RMS tank currentcontours (a) on the φ_(DC)=π plane for M=0.5 and (b) on the φ_(AB)=πplane for M=1.5. In FIG. 11, depicts the MCT as the solid curve andnormalized RMS tank current contours (a) on the φ_(DC)=π plane for M=0.5and (b) on the φ_(AB)=π plane for M=1.5. In FIG. 11, the MCT is plottedfor two different conversion ratios. In both plots, contours for thenormalized RMS tank current are plotted beneath the MCT. Following theMCT curve from right to left on either plot transitions from maximumforward power or current to maximum reverse power or current whilemaintaining the minimum possible RMS tank currents at any given power orcurrent level for the given conversion ratio. Converter tank parametervariations have minimal effect on the MCTs, allowing the sametrajectories to be used regardless of component tolerances in the finaldesign. This is due to the use of normalized variables in the derivationof the MCTs. Although tank parameter variations may affect the absolutevalue of tank currents and output power levels, the normalized valuesare unaffected leaving the MCTs unchanged.

It is useful to construct the tank phasor diagram as the operating pointmoves along the MCT from P_(OUT)=0 up to P_(OUT)=P_(OUT) ^(MAX). In whatfollows, the phasor associated with voltage v_(X)(t) is denoted withV_(X).

Let us discuss case M<1 first. For |U_(OUT)|<(1−M²)^(1/2), two operatingpoints Q_(γ+)(P_(OUT)) and Q_(γ−)(P_(OUT)) exist, as illustrated in FIG.11(a), respectively located on the γ₁₊ and γ¹⁻ branches of the MCT. Itis easy to prove that such two operating points are physicallyequivalent, i.e. they correspond to the same tank phasor diagram.Branches γ₁₊ and γ¹⁻, as well as branches λ₁₊ and λ¹⁻ for the M>1 case,are equivalent in this sense. FIG. 12 depicts phasor diagrams in forwardpower mode along the MCT, M<1 case along branches γ₁₊/γ¹⁻ (a) and alongbranch γ₂ (b). The typical phasor diagram corresponding to the condition0<U_(OUT)<(1−M²)^(1/2) is sketched in FIG. 12(a). Minimum currentoperation forces the tank current to be in phase with V_(DC)′; since thetank current is always orthogonal to V_(AB)−V_(DC)′, as the powerincreases the tip of phasor V_(AB) slides along the perpendicular to thetip of V_(DC)′, i.e. the triangle defined by V_(AB) and V_(DC)′ isrectangle. Along γ_(1±), minimum current operation for M<1 can thereforebe equivalently defined as the condition in which the output bridgedelivers the maximum voltage (φ_(DC)=180°) while angles φ_(AB) andφ_(AD) are modulated so as to maintain unity output power factor (i.e. Iin phase with V_(DC)′).

The phasor arrangement illustrated in FIG. 12(a) is maintained up to thepoint in which the magnitude of V_(AB) is maximized, i.e. up toφ_(AB)=180°. This condition, which occurs at |U_(OUT)|=(1−M²)^(1/2) aspredicted by (74), marks the separation between branches γ_(1±) andbranch γ₂. Above such power level, V_(AB) rotates at constant magnitudeas the power increases, and the tank current no longer stays in phasewith V_(DC)′; along γ₂, the phasor diagram appears as shown in FIG.12(b).

Reverse power operation (P_(OUT)<0) results in similar phasor diagrams,with the current phasor 180° phase-shifted with respect to FIG. 12 andV_(DC)′ now leading V_(AB).

Case M>1 can be discussed using similar arguments but with the roles ofthe two bridges exchanged. Along λ₁, minimum current operation for M>1can be equivalently defined as the condition in which the input bridgedelivers the maximum voltage (φ_(AB)=180°) while angles φ_(DC) andφ_(AD) are modulated so as to maintain unity input power factor (I inphase with V_(AB)). As predicted by (75), this condition can bemaintained up to |U_(OUT)|=(1−M⁻²)^(1/2). Beyond such point, the minimumcurrent trajectory proceeds along λ₂.

Case M=1 can be regarded, at this point, as a boundary situation inwhich no phasor arrangement exists to force the tank current I to be inphase with V_(AB) or V_(DC)′. This explains why only γ₂-like solutionsexist in this case, as described by either (74) or (75).

The foregoing phasor analysis provides an explanation for the existenceof different branches in the minimum current trajectories and of anintermediate power level above which the minimum current solutionchanges its analytical structure.

In this Section the switching behavior of the electronic devices whenthe DABSRC is operated along the minimum current trajectory isdiscussed. Only case M<1 is discussed in detail, as the symmetrical caseM>1 can be treated similarly by exchanging the roles of the two bridgesand by replacing M with 1/M in the analytical expressions.

Consider the phasor diagram illustrated in FIG. 12(b), corresponding to|U_(OUT)|>(1−M²)^(1/2), which implies φ_(AB)=φ_(DC)=180°. At these powerlevels, the tank current lags the input voltages V_(A) and V_(B), andleads output voltages V_(D) and V_(C). Hence, taking the sign of thedevice current at its turn-off instant as a simplified criterion todiscriminate between soft or hard turn-on switching, for|U_(OUT)|>(1−M²)^(1/2) all the electronic devices turn on atzero-voltage. As the power level decreases below |U_(OUT)|=(1−M²)^(1/2)and the operating point enters branches γ_(1±), phasor diagram shown inFIG. 12(a) is obtained, with the tank current in phase with the outputvoltage and the input bridge being modulated by φ_(AB). Therefore theoutput bridge tends to operate at the boundary between soft and hardswitching. As far as the input bridge is concerned, an analysis based onthe fundamental approximation predicts hard switching of the inputbridge devices at both turn-on and turn-off over a power intervaldefined by|U _(OUT)|≦√{square root over (M·(1−M))}  (76)

These results extend the analysis reported in [22], in which thezero-voltage switching boundary condition for the M<1 case was expressedas cos(φ_(AD))=M, here written according to the notation used in thispaper. From (67) and with φ_(AB)=φ_(DC)=180°, the corresponding criticalpower level is found to be |U_(OUT)|=(1−M²)^(1/2), which represents thebreaking point between the γ_(1±) branches and the γ₂ branch in theminimum current trajectory as predicted by (9.a). FIG. 13 depictstheoretical hard switching vs. soft switching boundary for the inputbridge in the M<1 case: comparison between one-angle modulation andminimum current trajectory. Below such power level, a one-anglemodulation like the one considered in FIG. 13 necessarily induces theoutput bridge into hard-switching operation. If, on the other hand, theoperating point follows the MCT along branches γ_(1±), the output bridgeis theoretically maintained at the soft/hard switching boundary. Suchadvantage comes at the price of the creation of a hard switchinginterval for the input bridge at light load, as indicated by (76).

Nonetheless, comparison between the hard switching vs. soft switchingboundaries along the one-angle modulation trajectory and along theproposed MCT shows, as illustrated in FIG. 13 for M<1, that the hardswitching interval along the MCT, given by (76), is consistently smallerthan on the one-angle modulation trajectory. The difference between thetwo boundaries represents the additional ZVS interval gained byoperating on the MCT rather than on the simple one-angle modulationpath. Furthermore, it is shown in Section V that input hard-switching onthe MCT is much less severe than hard-switching occurring along theone-angle trajectory.

IV.2 Gain Scheduling Feedback Control

Once steady state operating angles have been determined, a dynamiccontroller can be derived. Having previously generated small signalmodels relating control angle perturbations to input and output currentperturbations, the small signal relation between the output commandcontrol variable and the minimum current trajectory control angles stillmust be derived. Once this has been completed, a small signal model ofthe DABSRC controlled along the minimum current trajectories may beassembled. Using this model, loop gains are analyzed and used to designa feedback controller for input and output current control. Due to thenature of the open loop system controlled in this way, a gain scheduledfeedback controller is ultimately used.

In Section III.3 regarding small signal analysis of the DABSRC, transferfunctions relating each of the three control angles to either the inputor output current were derived. In order to control the DABSRC along theMCT, a small signal model must be derived relating the control inputU_(OUT) to the control angle vector. Once this relation has beenderived, a full small signal model of the DABSRC controlled along theMCT is complete.

From the trajectories in (74) and (75), only branches γ₁₊, γ₂, and λ₁₊will be used as they cover the whole control space. A similar derivationis possible if trajectories γ¹⁻, γ₂, and λ¹⁻ are chosen. The results aresymmetric if a 180° rotation around Φ_(AB)=π, Φ_(AD)=0 for M<1 andΦ_(DC)=π, Φ_(AD)=0 for M>1 is performed.

Taking the partial derivative of branches γ₁₊, γ₂, and λ₁₊ with respectto the command variable U_(OUT),

$\begin{matrix}{{A_{\varphi}\left( \gamma_{1 +} \right)} = \left\{ {\begin{matrix}{{A_{AB}\left( \gamma_{1 +} \right)} = \frac{\partial{\varphi_{AB}\left( \gamma_{1 +} \right)}}{\partial u_{out}}} \\{{A_{AD}\left( \gamma_{1 +} \right)} = \frac{\partial{\varphi_{AD}\left( \gamma_{1 +} \right)}}{\partial u_{out}}} \\{{A_{D\; C}\left( \gamma_{1 +} \right)} = \frac{\partial{\varphi_{D\; C}\left( \gamma_{1 +} \right)}}{\partial u_{out}}}\end{matrix},} \right.} & (77) \\{{A_{\varphi}\left( \gamma_{2} \right)} = \left\{ {\begin{matrix}{{A_{AB}\left( \gamma_{2} \right)} = \frac{\partial{\varphi_{AB}\left( \gamma_{2} \right)}}{\partial u_{out}}} \\{{A_{AD}\left( \gamma_{2} \right)} = \frac{\partial{\varphi_{AD}\left( \gamma_{2} \right)}}{\partial u_{out}}} \\{{A_{D\; C}\left( \gamma_{2} \right)} = \frac{\partial{\varphi_{D\; C}\left( \gamma_{2} \right)}}{\partial u_{out}}}\end{matrix},} \right.} & (78) \\{{A_{\varphi}\left( \lambda_{1 +} \right)} = \left\{ {\begin{matrix}{{A_{AB}\left( \lambda_{1 +} \right)} = \frac{\partial{\varphi_{AB}\left( \lambda_{1 +} \right)}}{\partial u_{out}}} \\{{A_{AD}\left( \lambda_{1 +} \right)} = \frac{\partial{\varphi_{AD}\left( \lambda_{1 +} \right)}}{\partial u_{out}}} \\{{A_{D\; C}\left( \lambda_{1 +} \right)} = \frac{\partial{\varphi_{D\; C}\left( \lambda_{1 +} \right)}}{\partial u_{out}}}\end{matrix}.} \right.} & (79)\end{matrix}$

TABLE 2 Small Signal Gains for Operation on the MCT MCT Small SignalGains A_(AB)(γ₁₊)$\frac{{- 2}U_{OUT}}{\sqrt{\left( {1 - M^{2} - U_{OUT}^{2}} \right)\left( {M^{2} + U_{OUT}^{2}} \right)}}$A_(AD)(γ₁₊)$\frac{M}{M^{2} + U_{OUT}^{2}} + {\frac{1}{2}{A_{AB}\left( \gamma_{1 +} \right)}}$A_(DC)(γ₁₊) 0 A_(AB)(γ₂) 0 A_(AD)(γ₂) $\frac{1}{1 - U_{OUT}^{2}}$A_(DC)(γ₂) 0 A_(AB)(λ₁₊) 0 A_(AD)(λ₁₊)$\frac{M}{1 + {M^{2}U_{OUT}^{2}}} + {\frac{1}{2}{A_{DC}\left( \lambda_{1 +} \right)}}$A_(DC)(λ₁₊)$\frac{{- 2}U_{OUT}}{\sqrt{\left( {1 - \left( \frac{1}{M} \right)^{2} - U_{OUT}^{2}} \right)\left( {\left( \frac{1}{M} \right)^{2} + U_{OUT}^{2}} \right)}}$results in nine gain terms. In (77)-(79) the partial derivatives of eachcontrol angle with respect to the output command are taken assuming thatthe control angle is on the trajectory given, with the resultssummarized in Table 2 above.

Using (77)-(79), piecewise linear gains are defined for each of thethree control angles depending on converter operating point,

$\begin{matrix}{A_{AB} = \left\{ {\begin{matrix}{M \leq {1\left\{ \begin{matrix}{{U_{OUT}} \leq {\sqrt{1 - M^{2}}\text{:}\mspace{14mu}{A_{AB}\left( \gamma_{1 +} \right)}}} \\{{U_{OUT}} \geq {\sqrt{1 - M^{2}}\text{:}\mspace{14mu}{A_{AB}\left( \gamma_{2} \right)}}}\end{matrix} \right.}} \\{M \geq {1\left\{ \begin{matrix}{{U_{OUT}} \leq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}\text{:}\mspace{14mu}{A_{AB}\left( \lambda_{1 +} \right)}}} \\{{U_{OUT}} \leq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}\text{:}\mspace{14mu}{A_{AB}\left( \gamma_{2} \right)}}}\end{matrix} \right.}}\end{matrix},} \right.} & (80) \\{A_{AD} = \left\{ {\begin{matrix}{M \leq {1\left\{ \begin{matrix}{{U_{OUT}} \leq {\sqrt{1 - M^{2}}\text{:}\mspace{14mu}{A_{AD}\left( \gamma_{1 +} \right)}}} \\{{U_{OUT}} \geq {\sqrt{1 - M^{2}}\text{:}\mspace{14mu}{A_{AD}\left( \gamma_{2} \right)}}}\end{matrix} \right.}} \\{M \geq {1\left\{ \begin{matrix}{{U_{OUT}} \leq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}\text{:}\mspace{14mu}{A_{AD}\left( \lambda_{1 +} \right)}}} \\{{U_{OUT}} \leq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}\text{:}\mspace{14mu}{A_{AD}\left( \gamma_{2} \right)}}}\end{matrix} \right.}}\end{matrix},} \right.} & (81) \\{A_{D\; C} = \left\{ {\begin{matrix}{M \leq {1\left\{ \begin{matrix}{{U_{OUT}} \leq {\sqrt{1 - M^{2}}\text{:}\mspace{14mu}{A_{D\; C}\left( \gamma_{1 +} \right)}}} \\{{U_{OUT}} \geq {\sqrt{1 - M^{2}}\text{:}\mspace{14mu}{A_{D\; C}\left( \gamma_{2} \right)}}}\end{matrix} \right.}} \\{M \geq {1\left\{ \begin{matrix}{{U_{OUT}} \leq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}\text{:}\mspace{14mu}{A_{D\; C}\left( \lambda_{1 +} \right)}}} \\{{U_{OUT}} \leq {\sqrt{1 - \left( \frac{1}{M} \right)^{2}}\text{:}\mspace{14mu}{A_{D\; C}\left( \gamma_{2} \right)}}}\end{matrix} \right.}}\end{matrix}.} \right.} & (82)\end{matrix}$

Using these three gains relating each control angle to the outputcommand, a final set of transfer functions is assembled to relate outputcommand variations directly to output current variations using equations(63)-(66),

$\begin{matrix}{\begin{matrix}{{\overset{\sim}{i}}_{OUT} = {{{\overset{\sim}{\varphi}}_{ab}i_{OUT}^{AB}} + {{\overset{\sim}{\varphi}}_{ad}i_{OUT}^{AD}} + {{\overset{\sim}{\varphi}}_{d\; c}i_{OUT}^{D\; C}}}} \\{= {{{\overset{\sim}{u}}_{out}A_{AB}i_{OUT}^{AB}} + {{\overset{\sim}{u}}_{out}A_{AD}i_{OUT}^{AD}} + {{\overset{\sim}{u}}_{out}A_{D\; C}i_{OUT}^{D\; C}}}} \\{= {{\overset{\sim}{u}}_{out}\left( {{A_{AB}i_{OUT}^{AB}} + {A_{AD}i_{OUT}^{AD}} + {A_{D\; C}i_{OUT}^{D\; C}}} \right)}}\end{matrix}.} & (83) \\{{H_{iout}(s)} = {\frac{{\overset{\sim}{i}}_{OUT}}{{\overset{\sim}{u}}_{out}} = {{A_{AB}i_{OUT}^{AB}} + {A_{AD}i_{OUT}^{AD}} + {A_{D\; C}{i_{OUT}^{D\; C}.}}}}} & (84)\end{matrix}$

Equation (84) is the desired result, as it allows control of the DABSRCusing an output command variable. Derivation of a transfer functionuseful for feedback control of the DABSRC using an input commandvariable follows the same steps as above, with all output quantitiesreplaced by the equivalent input quantity.

Mathematically the gains seen in Table 2 present a problem at the pointwhere the γ₁₊ and γ₂ trajectories touch for M<1 and at the point wherethe λ₁₊ and γ₂ trajectories touch for M>1. When these points areapproached from lower magnitude output command towards higher magnitudepower commands, the MCT begins to run parallel to contours of constantoutput command. At these points the small signal MCT gain reaches aninfinite value, requiring an infinite change in control angle to achievea change in output variable. The same phenomenon occurs at both themaximum and minimum output commands, for a similar reason. Althoughmathematically real and understandable, the effect is mitigated in areal system due to a number of non-idealities. The main consequence ofthis effect is that simulations must avoid these points in order toavoid non-finite transfer functions.

FIG. 14 depicts output command to output current transfer functionsplotted for a sweep from 90% reverse power to 90% forward power. Threedifferent conversion ratios are shown, from left to right M=0.4 stepdown, M=1 unity conversion ratio, and M=1.2 step up conversion ratio. InFIG. 14, (84) is plotted for three separate conversion ratios, M=0.4,M=1.0, and M=1.2. For each conversion ratio, the output current commandhas been swept from 90% of the full possible reverse current to 90% ofthe full possible forward current. In each case, output current commandswhich are near the points of infinite small signal MCT gain and at alower magnitude output level are shifted to lower powers such that thereis a 3% of maximum output current buffer around these regions on thelower magnitude current side. With these modifications, FIG. 14 avoidsincluding any anomalous operating points.

All plots exhibit a large spike in gain at a frequency equal to theswitching frequency of the converter minus the tank resonant frequencyas expected. Although located at the same frequency for all operatingpoints, the associated phase drop can be seen to vary across bothconversion ratio as well as output command. In addition to slight phasedifferences between operating points, a large variation in gain is seenin all plots, with both the low frequency gain as well as the resonantspike gain varying across both conversion ratio and output command.

Due to the variability in both gain and phase of the control to outputtransfer function (84) demonstrated in FIG. 14 a fixed controller ispoorly suited for control of the DABSRC when operated over a wide rangeof power levels and conversion ratios. To overcome this, a gainscheduled feedback controller is used. Fortunately the general shape ofthe bode plots in FIG. 14 remain fairly constant at frequencies belowthe switching frequency of the converter. This allows an integralcontroller with an operating point dependent gain to be used, as seen inFIG. 15. FIG. 15 a schematic block diagram of a gain scheduled feedbackloop for output current control. Three different conversion ratios areshown, from left to right M=0.4 step down, M=1 unity conversion ratio,and M=1.2 step up conversion ratio.

For applications which require a consistent response from the converterregardless of operating point, a gain schedule may be built whichmaintains a constant bandwidth regardless of operating points. With thisapproach, the worst case operating point is the operating point at whichthe lowest possible bandwidth is achieved while still maintaining phasemargin P_(M)≧P_(M) _(_) _(MIN) and gain margin G-_(M)≧G_(M) _(_) _(MIN)for stability. At all other operating points, integral gains K_(i) aresolved for which maintain the bandwidth found at the worst case point,BW_(SET). Although providing consistent response characteristics, thistype of gain schedule results in larger than needed gain and phasemargins over much of the operating space and a lower bandwidth thannecessary at most operating points.

In contrast to a gain schedule which maintains a constant bandwidth, again schedule may be derived which maintains a fixed phase or gainmargin across all operating points. With this type of a gain schedule,the maximum possible bandwidth at all points can be achieved whilemaintaining constant stability margins. While providing higherbandwidths than the previous approach, this type of controller resultsin a less consistent response characteristic as operating point isvaried. For either gain scheduling approach, a script may be used tocalculate a gain table based on scheduling variables U_(CMD) and M. Thistwo dimensional table is then referenced into using the converteroperating point in order to select the proper gain.

Contrasting these two gain scheduled controllers is a fixed gainapproach. In this case a single gain is solved to maintain stability atthe worst case operating point. At this single worst case operatingpoint, all three approaches provide the same response. As operatingpoint is varied, a fixed gain controller results in excessive stabilitymargins leading to low bandwidth responses, as well as an inconsistentresponse characteristic.

For the DABSRC design described above in Section III.2, a gain scheduleis derived which provides the maximum possible bandwidth at alloperating points. Stability is ensured by requiring a phase marginP_(M)≧55° and a gain margin G_(M)≧10 dB. The input voltage is againassumed to be V_(IN)=500 V, with conversion ratios between M=0.1 andM=1.2, corresponding to output voltages between V_(OUT)=50 V andV_(OUT)=600 V. FIG. 16 depicts Gain Schedule for a V_(IN)=500 V DABSRCderived for maximum converter bandwidth at all points. Integral gains(left) result in converter bandwidths (right). In FIG. 16 the resultinggains and bandwidths are seen. Integral gains vary between 1338 unitsand 3039 units, achieving a maximum bandwidth of 2.76 kHz. The worstcase operating point, found at a conversion ratio of M=1.2 andU_(CMD)=0.66 has a bandwidth of 1.33 kHz with an integral gain of 1338units. A fixed gain implementation would use the same integral gain asfound at this point, while a fixed bandwidth gain scheduleimplementation would result in a converter with a bandwidth of 1.33 kHzat all points. FIG. 17 depicts Gain Schedule phase margin for aV_(IN)=500 V DABSRC derived for maximum converter bandwidth at allpoints. In FIG. 17 the phase margins for a converter using the maximumbandwidth gain schedule controller are plotted. A constant gain marginof 10 dB is maintained throughout the operating space. The gain marginis the constraint limiting the controller gain while phase margins muchhigher than needed are seen, even though the controller results in themaximum bandwidth at all points. A more complex controller would be ableto solve this issue, but is unneeded either to prove the suitability ofthe approach or for the application focused on here.

Although small signal stability is maintained at all points by the gainschedule designed above, a large signal analysis of stability with thisapproach has not been performed.

IV.3 Multi-Mode Control

In order to add the ability to regulate output voltage and output powerto the current controlled DABSRC, multi-mode control is used. Not onlydoes this extension provide the needed voltage and power regulation, butit also allows for the series and parallel connection of multipleconverters into a single module with natural power sharing. Thisapproach uses a limit curve for each of the three control variables(power, voltage and current) in order to achieve the desired results.

An apparatus 7900 for multi-mode control of a converter is presented.The apparatus may be implemented with the converter 10 depicted in FIG.1 and may include a main power flow controller 215 and/or mastercontroller 295 implementing the multi-mode control apparatus. FIG. 18(a)depicts a multi-mode control output plane detailing of power, current,and voltage limit curves for a bidirectional converter. FIG. 18(b)depicts a modified limit curves to enable inherent power, voltage, andcurrent sharing. To visualize the interaction of the three limit curves,the output plane of the converter is typically drawn of converter outputcurrent and voltage as seen in FIG. 18(a). In forward power, theconverter regulates below the V_(SET) line, while in reverse power theconverter regulates above this line. The combination of these areasmakes up the shaded portion of the limit line curves in FIG. 18, anddefines the possible operating points for a converter dependent on theoutput load.

FIG. 79 is a schematic block diagram of one embodiment of a multi-modecontrol apparatus in accordance with one embodiment of the invention,which, in one embodiment, may be included with the main power flowcontroller 215. In one embodiment, the multi-mode control apparatus 7900includes a voltage regulation module 7902 that controls output voltageof a DC to DC converter to an output voltage reference V_(SET), whichmay be referred to as simply the voltage reference V_(SET), over anoutput current range between an operating condition where output powerof the converter reaches a positive power reference P_(SET), or simplypower reference P_(SET), and output power of the converter reaches anegative power reference −P_(SET). The converter is a bidirectionalconverter. In one embodiment, the converter is a resonant powerconverter 100. In another embodiment, the resonant power converterincludes at least one stage of a DABSRC. As depicted in FIG. 18(a), thevoltage regulation module may regulate the output voltage V_(OUT) to avalue represented by the horizontal line V_(SET).

The multi-mode control apparatus 7900 may also include a positive powerregulation module 7904 that controls output power P_(OUT) of theconverter to the positive power reference P_(SET) over a positiveconstant power range between the output voltage of the converter beingat the output voltage reference V_(SET) and output current I_(OUT) ofthe converter being at a positive output current reference I_(SET),which may be described simply as the current reference I_(SET). Asdepicted in FIG. 18(a), the positive power module may regulate outputpower P_(OUT) to the curved line by P_(SET) between V_(SET) and I_(SET).

The multi-mode control apparatus 7900 may also include a negative powerregulation module 7906 that controls output power P_(OUT) of theconverter to the negative power reference −P_(SET) over a constant powerrange between output voltage V_(OUT) of the converter being at theoutput voltage reference V_(SET) and a maximum negative power limit ofthe converter. For example, the negative power reference −P_(SET) may beset lower than the maximum negative power limit of the converter. Asdepicted in FIG. 18(a), the negative power module may regulate outputpower P_(OUT) to the curved line by −P_(SET) and increasing upward to avoltage higher than the voltage setpoint V_(SET). In one embodiment,polarity of power flow (positive or negative) is determined by comparingthe measured output voltage V_(OUT) to the voltage set point V_(SET)(0).If the measured voltage is greater than the set point, power flow ispositive. If the measured voltage is below the set point, the power flowis negative. A signal determining power flow polarity is shown in FIG.44, V_(sign). The current limit is set by using I_(SET) as the positiveand negative internal limit for the voltage and power loop compensators,as shown in FIG. 43. This way, only the voltage and power loop outputcurrent references need to be compared and inherently have the currentlimit built in, and the polarity is already correct for positive andnegative power flow. The final current reference used is found as shownin FIG. 46. The minimum of the absolute value of the current referencesfrom the voltage and power loops determines which loop to use, then theactual current references from the voltage loop (with sign) or the powerloop (with sign added in) are used.

The multi-mode control apparatus 7900 may also include a constantcurrent module 7908 that limits output current to a positive outputcurrent reference I_(SET) in a range between a minimum output voltageand output power P_(OUT) of the converter reaching the positive powerreference P_(SET). As depicted in FIG. 18(a), the vertical line on theright side next to I_(SET) may represent the constant current module7908 limiting the current to I_(SET). In one embodiment, the minimumoutput voltage is zero. In another embodiment, the minimum outputvoltage may be a different value, such as a minimum output voltage thatcan be controlled or maintained by the converter 10 and controls. One ofskill in the art will recognize other appropriate minimum outputvoltages.

Note that an input, i.e. 141 and an output, i.e. 143 may be a matter ofperspective. For example, the input 141 may be connected to a voltagesource and/or a load and the output may be connected to a load that iscapable of syncing and sourcing current so that in one mode the voltagesource provides power to the load and in another mode the load providespower to a load connected to the input 141 of the converter 10. In thisembodiment, the input and output may switch when the load provides powerto the converter 10. In this condition, the input and output of theconverter 10 may be reversed and FIG. 18(a) may apply to the new inputand output. In another embodiment, when power flows toward the input141, the converter output power P_(OUT) may follow a trajectory similarto the right side of FIG. 18(a) and the apparatus 7900 may include anegative current setpoint −I_(SET). For example, the constant currentmodule 7908 may further limit the output current I_(OUT) to a negativeoutput current reference −I_(SET) in a range between a minimum outputvoltage and output power of the converter reaching the negative powerreference −P_(SET). For example, the constant current module 7908 maylimit the output current I_(OUT) to a negative output current reference−I_(SET) as shown in FIG. 18(a) where the converter 10 may follow thepath on the left end of the control diagram of FIG. 18(a).

In one embodiment, the constant current module 7908 includes a currentfeedback control loop that limits output current I_(OUT) to below thepositive output current reference I_(SET). In another embodiment, thepositive power regulation module 7904, the negative power regulationmodule 7906, and the voltage regulation module 7902 include feedbackcontrol loops and the current feedback control loop is an inner feedbackcontrol loop and the feedback control loops of the positive powerregulation module 7904, the negative power regulation module 7906, andthe voltage regulation module 7902 make up an outer feedback loop. Thecurrent feedback loop is discussed below. One implementation of thecontrol loops is depicted in FIG. 19. FIG. 19 is a schematic blockdiagram of one embodiment of a multi-mode control (“MMC”) control loopsshowing a current regulated converter with an internal current feedbackloop, as well as a power and voltage outer feedback loops. Feedbackcontrollers C_(V)(s) and C_(P)(s) provide improved voltage and powerregulation respectively.

In one embodiment, the constant current feedback loop includescompensation implemented using a gain scheduled feedback controller, asdescribed above in Section IV.2 and may be configured as shown in FIG.15. The gain scheduled feedback controller includes one or more outputcontrol signals that vary over a plurality of control regions. The gainscheduled feedback controller implements a different compensationequation for each control region. In another embodiment, the converter10 includes one or more phase shift modulators 230 controlled by the oneor more output control signals 280, where the one or more output controlsignals 280 control according to a MCT control technique. The MCTsubstantially minimizing circulating current within the converter 10. Asused herein, substantially minimizing circulating current within theconverter 10 includes following an MCT trajectory or following atrajectory that is close to the MCT. For example, substantiallyminimizing circulating current within the converter 10 may includeoperating the converter 10 as depicted in FIG. 33 or may includeoperating the converter 10 so that one or more switching legs follow anMCT or a trajectory as depicted in FIG. 33. One of skill in the art willrecognize other ways to substantially minimize circulating current. Inanother embodiment, the gain scheduled feedback controller maintains theconverter in a ZVS region while minimizing circulating current byfollowing a trajectory a fixed distance from an MCT, such as depicted inFIG. 33.

In one embodiment, the output voltage reference V_(SET) varies withoutput current I_(OUT) such that the output voltage reference V_(SET)decreases as output current I_(OUT) increases. In another embodiment,the positive output current reference I_(SET) varies with output voltageV_(OUT) such that the positive output current reference I_(SET), whichmay also be referred to herein as the converter current reference,decreases as output voltage V_(OUT) increases. Operation of a modulealong a current limit curve may result in converter power sharing aslong as all converters in a module are connected in parallel. Seriesoperation of current limited converters may prove problematic in certainembodiments, as this leaves each individual converter with anuncontrolled output voltage. A simple approach with no communicationbetween modules is to use droop control by adding a slope to the currentlimit line (FIG. 18(b)). Representing this slope with resistance R_(I)the converter current reference I_(Set) is written as a function of theconverter output voltage V_(OUT),

$\begin{matrix}{{I_{Set}\left( V_{OUT} \right)} = {{I_{Set}(0)} - {\frac{V_{OUT}}{R_{I}}.}}} & (85)\end{matrix}$

When a module made up of series connected converters is operated incurrent regulation mode, the output voltage of any two converters may bemismatched by as much as the full module voltage, such that a singleconverter processes the full module power. The addition of R_(I) reducesthis theoretical maximum converter voltage offset when operated inseries, ∥ΔV_(S)∥, to∥ΔV _(S) ∥=R _(I) ΔI _(ε),  (86)where ΔI_(ε) represents the maximum current sensing error betweenconverters.

Operation along a voltage limit line achieves inherent power sharing inmodules made up of series connected converters, while parallel connectedconverters in a voltage regulating module are left with an uncontrolledoutput current. This issue is solved with the introduction of a slope onthe voltage limit line (FIG. 18(b)), represented as R_(V). Theintroduction of this slope allows the converter output voltage referenceV_(Set) to be written as a function of the converter output currentI_(OUT),V _(Set)(I _(O))=V _(Set)(0)−I _(OUT) R _(V).  (87)

Without R_(V) parallel connected converters regulating voltage may havean output current offset equal to the full current processed by themodule. R_(V) reduces this theoretical maximum converter currentdifference when operated in parallel, ∥ΔI_(P)∥, to

$\begin{matrix}{{{\Delta\; I_{P}}} = {\frac{1}{R_{V}}\Delta\;{V_{ɛ}.}}} & (88)\end{matrix}$

When operating on the power limit curve, automatic power balance of bothparallel and series converters are achieved naturally. As allinterconnected converters in a single module share a common voltage(parallel connection) or a common current (series connection), allconverters in that module regulate to the same operating point whengiven equal power commands. For power limit control the maximumdifference in converter power processing is simply equal to theconverter power sensing accuracy.

In a practical application, the voltage mode slope R_(V) is a smallvalue (ideally 0Ω), while the current mode slope R_(I) is a large value(ideally infinite).

To simplify the extension of MMC to bidirectional converters it isassumed that symmetrical limit curves are used, such that the maximumforward current and power are the same as the maximum reverse currentand power. The converter output voltage is assumed to remain positive.

FIG. 18 depicts multi-mode control loops showing a current regulatedconverter with an internal current feedback loop, as well as a power andvoltage outer feedback loops. Feedback controllers C_(V)(s) and C_(P)(s)provide improved voltage and power regulation respectively. Convertersthat make up a module are assumed to have a well-designed internalcurrent regulation loop already implemented. This internal feedback loopprovides output current regulation with a high, constant bandwidth,which has been designed to meet all system specifications. The existenceof this internal feedback loop greatly simplifies the design of theouter voltage and power feedback loops. Each of these loops need onlyact on the well behaved inner loop, which in many cases can berepresented as a single pole system. A block diagram for this setup isseen in FIG. 19. MMC follows by generating an appropriate currentreference for each mode. The operation mode is selected by determiningthe minimum of the absolute values of the three references. Thecorresponding mode is the one that regulates.

While operating in current regulation mode, the appropriate convertercurrent reference is simply I_(Set)(V_(OUT)),I _(Ref) ^(i) =I _(Set)(V _(OUT)).  (89)

No additional compensator is needed, as the converter internal feedbackloop already exists.

Using (87) and (89) for voltage and current reference points,controllers C_(V)(s) and C_(P)(s) in FIG. 19 can be derived in order tocomplete MMC of the DABSRC either as a stand-alone converter, or as asingle converter in a module of multiple converters with arbitraryoutput topology.

The error signal for voltage regulation is the difference between thedesired V_(Set) value and the measured output voltage, V_(OUT). Theaddition of a voltage regulating compensator, C_(V)(s) results in acurrent reference for voltage regulation ofI _(Ref) ^(v) =C _(V)(V _(Set) −V _(OUT)).  (90)

FIG. 20 is a schematic block diagram of a voltage regulation loop formulti-mode control of the DABSRC. The voltage regulation loop isdependent on the converter output impedance, and can be drawn as seen inFIG. 20. The loop gain T_(V)(s) can be written asT _(V)(s)=C _(V) H _(iout)(Z _(O) +R _(V)).  (91)

Feedback control of a current regulated converter along a power limitline is complicated by the nonlinear relation between output current andoutput power P_(OUT). Although a number of methods exist for dealingwith nonlinear feedback loops, one solution is to simply linearize theelement. For the system in question the resulting linearized outputcurrent to output power gain K_(V) becomes dependent on the three setpoints such that it exists within a range

$\begin{matrix}{{2Z_{O}\frac{P_{Set}(0)}{V_{Set}(0)}} \leq K_{V} \leq {2Z_{O}{{I_{Set}(0)}.}}} & (92)\end{matrix}$

In general this is not ideal as the power regulation controller must bedesigned at the worst case point operating point. With this highlyvariable gain in the feedback loop, this will likely require an overlyconservative controller design.

FIG. 21 is a schematic block diagram of a linearized power regulationloop for multi-mode control of the DABSRC. In situations where the threelimit lines change very little, this worst case controller may not be abad choice. In other situations, a better option is to pre-scale thecontrol effort in order to remove this set point dependence. This simpleform of gain-scheduling can be achieved by dividing the controller gainby twice the output current magnitude, as seen in FIG. 21. This solutionis easily implemented in a digital controller, and so is the preferredapproach.

The loop gain for this setup takes the formT _(P)(s)=C _(P) H _(iout) Z _(O).  (93)Assuming that R_(V) is small in comparison with the worst case outputimpedance, both the voltage loop and the power loop gain are the same ifthe gain-schedule method previously discussed is adopted for powercontrol. In this case only one controller needs to be derived.

Only a voltage controller is derived as it was shown above that the samecontroller may be used for both voltage and power regulation assumingsmall R_(V). This controller is then used for the power control loop aswell without further modification.

The voltage regulator is designed to provide a bandwidth of 2 kHz underthe worst case load using a second order controller. Assuming an outputcapacitance of 10 μF, this results in f_(z1)=728 Hz, f_(z2)=1.15 kHz,and A_(V)=0.025, with f_(P) set to a suitably high frequency of 10f_(z1). The controller is then converted into a digital form using abilinear transform with frequency pre-warping at the desired crossoverfrequency of 2 kHz. The resulting Z-domain controller takes the form

$\begin{matrix}{{C(z)} = {2.17 \times 10^{- 2}{\frac{\left( {z - 0.96} \right)\left( {z - 0.93} \right)}{\left( {z - 1.00} \right)\left( {z - 0.63} \right)}.}}} & (94)\end{matrix}$

The controller in (94) is designed to achieve a bandwidth ofapproximately 10 times less than the current regulation internal loop.When used with the gain scheduled approach seen in Section VI.2discussing a gain scheduled feedback controller this approach allows theexternal voltage and power loops to achieve high bandwidth as well.

V. Zero Voltage Switching Techniques for the DABSRC

A large variety of auxiliary circuitry aimed at ensuring soft-switchinghave been developed. These circuits can for the most part be groupedinto two categories: passive (commonly using magnetizing inductance orshunt circuitry methods) and active (using active switching networks oradvanced control schemes). Passive schemes have the benefit of little tono additional control complexity, while active auxiliary circuitryallows feedback and/or feed forward control of soft-switchingassistance. This additional control freedom can translate to lowerlosses and higher system efficiency at the cost of increased controlcomplexity.

Five different ZVS methods warrant consideration for the DABSRC. Theseinclude modifying tank magnetics in order to increase magnetizinginductance, two different forms of auxiliary leg assistance, inductivelylinking converter modules, and modifying the MCT in order to extend thenatural ZVS regions of the converter.

Modifying tank magnetics requires reducing the magnetizing inductance ofthe isolation transformer in FIG. 2B. This reduction in magnetizinginductance causes extra circulating currents in the resonant tank whichhave the effect of increasing the ZVS range for some switches in theDABSRC. This technique may be applied in order to provide ZVS assistanceto either the input bridge or the output bridge of the DABSRC foroperation around a specific operating point but comes at the cost ofincreased tank currents and therefore increased conduction losses. Theneed to design for a specific operation point makes this approach a poorchoice for systems which require operation over a wide range of powerlevels and conversion ratios. Additionally, the larger size andcomplexity of the tank transformer required for this approach makes itunattractive for a high power high density system.

Auxiliary legs used for ZVS assistance may be controlled in one of twoways. The first involves PWM control of the inductively linked auxiliaryhalf-bridge switches in order to store energy needed for ZVS transitionof the main switches. A resonant transition then discharges the inductorcurrent into the main switch node in order to achieve ZVS. By relying onthe resonant transfer of energy, this approach requires the main switchnode capacitance to be well known. Due to the nonlinear nature of manyswitching devices output capacitances, this approach is suited only forconverters which utilize relatively large additional switch nodecapacitance in order to slow down switching transitions. Additionally,this approach does not allow ZVS of the auxiliary switches turn ontransition, and so is poorly suited for high voltage applications.

Similar to PWM control of auxiliary legs, phase shift modulated (PSM)control may also be used. This approach generates a trapezoidal currentin the auxiliary inductor of sufficient magnitude to force ZVS of themain switch node. While larger RMS currents are required in theauxiliary inductor for this approach, its lack of dependence on aresonant transition makes it easier to control. In addition, ZVStransitions for all switching elements are achieved. For these reasonsit is a more attractive option for ZVS assistance of higher voltageDABSRCs which do not employ extra switch node capacitance.

If multiple converters are operated together as a module, either theprimary or secondary legs of two such converters may be inductivelylinked. The analysis of this approach is the same as for PSM auxiliarylegs, with the added condition that both legs of the bridge beingassisted will receive the same auxiliary current. Although thisrequirement may lead to excessive currents in one leg of each of thelinked converters, it can be successfully employed when used incombination with other ZVS methods. One such approach which synergizeswell is the use of modified MCTs.

In this chapter, the use of PSM auxiliary legs for ZVS assistance willbe focused on first. This approach provides the most flexible ZVSassistance and does not lead to excessive conduction losses due tolarger than needed current if controlled properly. A hybrid approachusing inductively linked converters to provide primary side ZVS andmodified MCTs for secondary side ZVS is described next.

V.1 PSM Leg ZVS Assistance Modeling

The phase shift modulated half-bridge (PSM-HB), also known as theauxiliary resonant pole (“ARP”) is one type of active soft-switchingassistance circuit specifically useful for maintaining zero voltageswitching of half- and full-bridge switch networks. Analysis of thismethod focuses first on a single pair of half-bridge switch networkslinked through an inductor. Although specifically focusing on PSMauxiliary legs, much of the same analysis is applicable to inductivelylinked converters.

FIG. 22 depicts half-bridge switching where switches Q₁ and Q₂ areassumed to operate at a fixed frequency, f_(s). Q₁ may be referred to asa first main switch and Q₂ may be referred to as a second main switch.Additionally, a duty cycle of d=0.5 is maintained, and a small dead timet_(d)<<T_(s) is used between switching transitions. Ensuring ZVS of ageneral MOSFET switching device requires that the voltage across thedevice reaches zero prior to device turn on. For switches in ahalf-bridge configuration driven as defined in FIG. 22, this requiresthat sufficient current be present during the dead-time betweenswitching events such that the switch node capacitance can be fullydischarged (for a lower switch) or charged (for an upper switch) beforethe next switching event. If natural switch node current of theconverter i_(x)(t) cannot accomplish this voltage commutation, anauxiliary half bridge connected in parallel with the first and coupledthrough an inductor (FIG. 23) can be used.

FIG. 23 is a schematic block diagram of one embodiment of a PSMhalf-bridge consisting of switches Q₁′ and Q₂′ connected to an existingconverter half-bridge (Q₁ and Q₂) through auxiliary inductor L_(aux) foractive ZVS assistance of Q₁ and Q₂. Q₁′ may be referred to as a firstauxiliary switch and Q₂′ may be referred to as a second auxiliaryswitch.

In one embodiment, the converter 10 may include an assisted ZVS Napparatus 2300 with a first auxiliary switch Q₁′ connected to a positiveconnection of a switching leg of the converter 10. In FIG. 23, thepositive connection point voltage is V_(A). The switching leg includes afirst main switch Q₁ and a second main switch Q₂ and the first andsecond main switches Q₁, Q₂ are connected at a main switch midpointV_(N). The assisted ZVS apparatus 2300 includes a second auxiliaryswitch Q₂′ connected between a negative connection of the switching legand the first auxiliary switch Q₁′, Q₂′, where a connection pointbetween the first and second auxiliary switches Q₂′ is an auxiliarymidpoint V_(N)′. The assisted ZVS apparatus 2300 includes an auxiliaryinductor L_(aux) connected between the auxiliary midpoint V_(N)′ and themain switch midpoint V_(N). The main switch midpoint V_(N) is alsoconnected to elements of the converter 10 in addition to the first andsecond main switches Q₁ and Q₂ and the auxiliary inductor L_(aux).

The first and second main power switches Q₁ and Q₂ turn on and off aspart of operation of the converter 10 and the first main switch Q₁includes a first capacitance C_(N1) and the second main switch Q₂includes a second capacitance C_(N2). In one embodiment, the firstcapacitance C_(N1) and second capacitance C_(N2) may be referred to asC_(N) and may be a same value. The assisted ZVS apparatus 2300 includesa switch regulation module 2302 that regulates switching of the firstand second auxiliary switches Q₁′, Q₂′ to control current i_(aux) in theauxiliary inductor L_(aux). The auxiliary inductor L_(aux) provides orremoves charge from the first capacitance C_(N1) and the secondcapacitance C_(N2) to adjust voltage across the first main switch Q₁ andthe second main switch Q₂ to induce zero voltage switching for the firstand second main switches Q₁, Q₂.

In one embodiment, the first capacitance C_(N1) is capacitance of thefirst main switch Q₁ and/or a capacitor connected in parallel with thefirst main switch Q₁. In addition, the second capacitance C_(N1) iscapacitance of the second main switch Q₂ and/or a capacitor connected inparallel with the second main switch Q₂. In another embodiment, theassisted ZVS apparatus 2300 includes a current sensing module 2304 thatsenses current i_(aux) in the auxiliary inductor L_(aux) and sensescurrent i_(x) in the connection between the elements of the converter 10and the main switch midpoint V_(N), where the switch regulation module2302 uses current sensed by the current sensing module 2304 andswitching states of the first and second main switches to regulateswitching in the first and second auxiliary switches to adjust currentin the auxiliary inductor to adjust voltage across the first and secondmain switches Q₁, Q₂ to achieve zero voltage switching.

FIG. 24 depicts PSM-HB waveforms, showing ZVS assistance current flowingin the correct direction for ZVS at both Q₁ and Q₂ turn on. In oneembodiment, the switching regulation module 2302 controls i_(aux) in theauxiliary inductor L_(aux) by controlling a phase angle Φ_(N) between avoltage transition at the auxiliary midpoint V_(N)′ and the main switchmidpoint V_(N). Φ_(N) is used to control the amount of ZVS assistancecurrent, i_(AUX). Assuming that main converter switches Q₁ and Q₂ inFIG. 23 are driven with a 50% duty cycle and small dead time t_(d) asseen in FIG. 22, applying a phase shift Φ_(N) between the main halfbridge and the auxiliary half bridge composed of Q₁′ and Q₂′ results ina trapezoidal auxiliary inductor current i_(aux)(t) through inductorL_(aux) as shown in FIG. 24. The peak value of this waveform i_(AUX) isadded with alternating sign to i_(x)(t) during each switch transition.Properly controlled, this additional current is the mechanism by whichPSM-HB circuitry assists ZVS transitions in devices Q₁ and Q₂.

For a converter with switching period T_(s) and dead time t_(d)<<T_(s),the approximate peak value of the auxiliary inductor current i_(aux)(t)can be written as a function of the phase shift between the mainhalf-bridge and the auxiliary half-bridge Φ_(N),

$\begin{matrix}{i_{AUX} \approx {\frac{\Phi_{N}}{4\pi\; f_{s}}{\frac{V_{A}}{L_{aux}}.}}} & (95)\end{matrix}$

Phase shift Φ_(N) is limited to angles between −π and +π, with maximumassistance current delivered at either limit. Positive and negativephase shifts are symmetric in terms of ZVS assistance under assumption(95), so that Φ_(N) can be constrained to the region between 0 and +π inorder to simplify analysis without losing generality.

To ensure that ZVS is achieved across the full operating range ofinterest for Q₁ and Q₂, L_(aux) must be designed such that at maximumpeak auxiliary current, with Φ_(N)=+π the worst case, switch nodecurrents can be compensated for by i_(aux)(t). The converter of interestdetermines how the worst case switch node current is found, but for ageneral switch node current of i_(x)(t) with positive current needed toachieve ZVS, L_(aux) can be approximated with the inequality

$\begin{matrix}{{L_{aux} \leq {\frac{1}{4f_{s}}\frac{V_{A}}{\left( {\frac{2C_{N}V_{A}}{t_{d}} - {\min\limits_{W_{x}}\left\lbrack {\frac{- 1}{t_{d}}{\int\limits_{t_{d}}i_{x}}} \right\rbrack}} \right)}}},} & (96)\end{matrix}$where W_(x) is the operating region of interest over which the assistedconverter (Q₁ and Q₂) will operate, and V_(A) is the bridge voltage asseen in FIG. 23. If (96) results in a negative inductance, ZVSassistance was never needed in the first place as the converternaturally achieves soft switching transitions. In one embodiment, theswitching regulation module 2302 controls the phase angle Φ_(N)according to (96).

For L_(aux) satisfying (96), ZVS is possible at all operating pointsbased on the phase angle Φ_(N). Phase angles smaller than necessary leadto hard switching of Q₁ and Q₂, while phase angles larger than neededlead to excessively high conduction losses in L_(aux), Q₁′, and Q₂′. Inorder to minimize the overall losses of the system, Φ_(N) must beregulated as close to its minimum value as possible while stillproducing the needed auxiliary assistance current peak. Beginning withthe above analysis, this minimum value may be calculated directly.

To ensure complete soft transitions in the switch node voltage V_(N)from FIG. 23 during the Q₁/Q₂ dead time t_(d), the sum of currentsi_(aux)(t) and i_(x)(t) must deliver sufficient charge to fullycommutate the switch node voltage before the next switching event. For abus voltage of V_(A) and a total output capacitance C_(N) on eachswitching device, this results in the inequality

$\begin{matrix}{{{\lambda{\int\limits_{t_{d}}{\left( {{i_{aux}(t)} + {i_{x}(t)}} \right){\mathbb{d}t}}}} \geq {2C_{N}V_{A}}},} & (97) \\{\lambda = \left\{ {\begin{matrix}{+ 1} & Q_{1} \\{- 1} & Q_{2}\end{matrix}.} \right.} & (98)\end{matrix}$

Assuming that i_(aux)(t)≈i_(AUX) throughout the dead time simplifies theanalysis, and after substituting (95) into (97) allows the control anglenecessary for ZVS to be written as a function of known constants andunknown converter parameters,

$\begin{matrix}{\Phi_{N} \geq {\frac{4\pi\; f_{s}L_{aux}}{t_{d}}{\left( {{2C_{N}} - {\frac{\lambda}{V_{A}}{\int\limits_{t_{d}}{{i_{x}(t)}{\mathbb{d}t}}}}} \right).}}} & (99)\end{matrix}$

Note that Φ_(N) ideally maintains the same value for both Q₁ and Q₂regardless of λ, as i_(x)(t) is assumed approximately half-periodanti-symmetric such that λi_(x)(t) maintains the same sign for both Q₁and Q₂.

All quantities in (99) are well known except for the integral of theconverter current into the node over the dead time t_(d). Although thisvalue may be approximated well with various methods, it is hard toachieve the accuracy needed due to unmolded ringing and other effects.In order to avoid this issue, the left had side of (97) may be directlycalculated with the use of an analog windowed integration circuit. Theresult of this analog integration is compared with a voltage dependentreference value equal to the right hand side of (97) to determine ifmore or less ZVS assistance is needed in order to soft-switch Q₁ and Q₂.This method does not require knowledge of i_(x)(t), and uses a referencewhich is easily computed or found experimentally. For a constant V_(A),the voltage dependent reference is constant and is used as the feedbackreference variable when designing a feedback controller for ZVSassistance. The use of this constant feedback reference greatlysimplifies controller implementations.

FIG. 25 is a schematic block diagram of a PSM-HB integration circuit fordirect measurement of charge delivered during the dead time betweenswitching events. A sample and hold ADC is used for digital controllerimplementations, while a peak detection circuit is used for completelyanalog loop design. FIG. 25 presents an example integration circuit fordirect measurement of the left hand side of (97). A current sensetransformer with turns ratio 1:n is attached to the switch node of themain converter half-bridge such that the sum of i_(aux)(t) and i_(x)(t)are sensed. The sense transformer is then loaded with a resistor bridgeof value R_(s). The voltage across this resistor bridge is integratedwith a differential op-amp using capacitors C_(q). To achieve thedesired window and reset, a set of four discrete switches are placedaround the integration op-amp. One pair of switches is used toenable/disable integration, while a complimentary pair is used to resetthe integration capacitor C_(q). These four switches are driven by asingle control signal S_(a) and its inverse S _(a). To achieveintegration during the dead time and reset afterwards, S_(a) is derivedfrom the gate drive signals of Q₁ and Q₂,S _(a)=!(GD[Q ₁ ]|GD[Q ₂]).  (100)

The resulting output voltage of the windowed integration circuit V_(s)is a scaled representation of the integrated switch node current on theleft side of (97)

$\begin{matrix}{V_{s} = {\frac{\lambda\; R_{s}}{{nR}_{f}C_{q}}{\int\limits_{t_{d}}{\left( {{i_{aux}(t)} + {i_{x}(t)}} \right){{\mathbb{d}t}.}}}}} & (101)\end{matrix}$Using (101) as the feedback variable, the right hand side of (97) isscaled accordingly to provide the feedback reference,

$\begin{matrix}{Q_{REF} \geq {2\frac{R_{s}C_{N}}{{nR}_{f}C_{q}}{V_{A}.}}} & (102)\end{matrix}$

FIG. 26 depicts a simple PSM-HB modulation (a) that applies phase anglechanges in a single step, introducing non-zero average auxiliarycurrent. Half-step-first modulation (b) avoids this, and achieves thedesired i_(AUX) in at most a single cycle. The transfer function ofinterest for feedback control of the PSM-HB relates the phase angleinput Φ_(N) to the ZVS assistance peak current i_(AUX). Using (95) asmall change in phase shift, ΔΦ_(N), is applied directly to the PSM-HBin order to create a small change in peak auxiliary current Δi_(AUX).This simple modulation scheme, seen in FIG. 26(a), results in animmediate average current offset. This offset can either be dealt withactively by modifying the PSM-HB gate drive signals according to anadditional average inductor current control loop, or passively byrelying on the dynamics of the PSM-HB to eventually cause near zeroaverage current to return.

To avoid perturbations in the average auxiliary current, a modulationtechnique can be used that directly modifies the peak-to-peak currentwithout perturbing the average inductor current. One method thatachieves this is ‘half-step-first’ modulation. Seen in FIG. 26(b), thismodulation strategy achieves the desired Δi_(AUX) in at most oneswitching period and greatly simplifies control analysis of the PSM-HB.This technique has the added benefit of achieving the desired auxiliarycurrent during converter cold startup in the first half period, thusavoiding hard switched turn on of the main switching elements.

Using half-step-first phase angle updates, PSM-HB phase modulation isanalyzed as a completely digital system composed of a scaled delay of atmost one switching period. The linearized small signal gain relatingΦ_(N) and i_(AUX) is derived by differentiating (95) with respect toΦ_(N). To simplify analysis, a constant single cycle delay formodulation is assumed. This will at worst cause control margins to belarger than expected, and is a reasonable assumption for manyimplementations of the phase modulator. The PSM-HB transfer function canbe defined with sample frequency f_(s) as

$\begin{matrix}{{H_{PSM}\lbrack z\rbrack} = {\frac{V_{A}}{4\pi\; f_{s}L_{aux}}{z^{- 1}.}}} & (103)\end{matrix}$

The current integration scheme described above can be analyzed as asensor gain relating the switch node currents during the Q₁/Q₂ dead timeand the total change delivered to the switch node as a scaled voltage.Assuming a capacitor C_(q) is used to integrate the node current, thecurrent integration gain can be approximated as

$\begin{matrix}{{{A_{q}\lbrack z\rbrack} = {\frac{t_{d}R_{s}}{{nR}_{f}C_{q}}z^{- 1}}},} & (104)\end{matrix}$using the circuit parameters defined in FIG. 25. Note that in (104) asample rate of 2f_(s) is assumed as a new sample is available after eachof the two node transitions which occur during any given switchingperiod. The output of this block is a voltage representing the totalcharge delivered to the switch during its dead time, scaled by theintegration circuit parameters.

The samples returned by the current integration circuitry alternatebetween the Q₁ and Q₂ device currents with a sample frequency of 2f_(s).In poorly matched systems, this may cause oscillations between twovalues at the output of the current integrator even in steady state. Theaddition of a running two sample minimum block after the integratorsafely solves this issue if needed, and can be acceptably modeled formost analysis by an additional single sample (one half switching period)delay added to (103). This has the additional effect of simplifyingcontrol loop analysis, as both (102) and a modified (103) have commonsample rates of f_(s) after making this assumption.

FIG. 27 is a schematic block diagram of one embodiment of a control loopblock diagram for the PSM-HB. i_(x)(t) is assumed to have a constantsign, and the auxiliary current during the dead time is assumed to beequal to the peak auxiliary current i_(AUX). Treating the natural switchnode current i_(x)(t) as a disturbance, the PSM-HB is analyzed using theblock diagram in FIG. 27. Loop gains for both charge reference as wellas natural switch node current disturbance are the same,T _(PSM) =C _(p) |[z]H _(PSM) [z]A _(q) [z],  (105)although the closed loop transfer functions differ. For chargereference, the closed loop transfer function is derived as

$\begin{matrix}{{C_{{CL}\_ Q} = \frac{{C_{p}\lbrack z\rbrack}{H_{PSM}\lbrack z\rbrack}}{1 + T_{PSM}}},} & (106)\end{matrix}$while the closed loop disturbance transfer function becomes

$\begin{matrix}{C_{{CL}\_ X} = {\frac{1}{1 + T_{PSM}}.}} & (107)\end{matrix}$The two transfer function found in (106) and (107) are the desiredresult, allowing feedback control of PSM-HB ZVS assistance.

When ZVS assistance is not needed in the main converter, it is desirableto minimize the conduction losses in the auxiliary inductance added bythe PSM-HB assistance circuitry. By setting Φ_(N) to zero, PSM-HBconduction losses may be eliminated, although such an approach causesPSM-HB auxiliary devices to hard switch causing large switching lossesespecially at higher switching frequencies. A better approach is tomaintain a minimum current in the PSM-HB at all times, such thatconduction losses are minimized while soft-switching is maintained. Toensure this, a minimum control angle, Φ_(Min), should be set such that

$\begin{matrix}{\Phi_{N} \geq \Phi_{Min} \geq {\frac{8\pi\; f_{s}C_{A}L_{aux}}{t_{dA}}.}} & (108)\end{matrix}$

In (108), the PSM half-bridge switches are assumed to have an outputcapacitance of C_(A), and a dead time of t_(dA). By using devices withsmall output capacitance, and letting t_(dA) be relatively large,Φ_(Min) can be kept small resulting in a small i_(AUX) and reducedoverhead losses when the main converter does not need ZVS assistance.This result is one argument for selecting PSM-HB devices with smalloutput capacitances. Unfortunately, small output capacitance MOSFETdevices are likely to have larger on-state resistances making it unclearwhich parameter should be focused on in device selection.

To help clarify the situation, the RMS value of the minimum i_(aux)(t)needed based on (108) for PSM-HB ZVS operation can be calculated as afunction of circuit parameters,

$\begin{matrix}{{{RMS}\left\lbrack i_{aux}^{MIN} \right\rbrack} = {\frac{2C_{A}V_{A}}{t_{dA}}{\sqrt{1 - {\frac{16}{3}\left( \frac{f_{s}C_{A}L_{aux}}{t_{dA}} \right)}}.}}} & (109)\end{matrix}$

As conduction losses are proportional to the square of (109), we can seethat conduction losses are approximately proportional to the square ofthe output device capacitance. When compared with the linear relationbetween losses and on-state resistance, it becomes clear that PSM-HBauxiliary devices with minimum output capacitance should be chosen overdevices with smaller on-state resistance. Selecting devices in this waywill reduce losses introduced by the use of PSM-HB ZVS assistance.

When designed such that the maximum i_(AUX) needed is achieved atΦ_(N)=π, the RMS and peak currents handled by the PSM-HB switchingdevices are in many cases much smaller than those handled by the mainconverter. For the best case design, the maximum RMS current handled bythe PSM-HB switching devices is

$\begin{matrix}{{{RMS}\left\lbrack i_{aux}^{MAX} \right\rbrack} = {\frac{i_{AUX}}{\sqrt{3}}.}} & (110)\end{matrix}$

For many converters, this means that much smaller devices may be usedfor the PSM-HB than for the main converter components as i_(AUX) is onlyequal to the peak worst-case current experienced by the main switchesdevices, not the total current handled by the main switching devices.Voltage stresses for both auxiliary devices and main switching elementswill remain the same, while the power loss in the auxiliary switcheswill be significantly lower than the main switches due to the reducedcurrents they must handle. The lower power loss experienced by thesedevices allows less effort and space to be spent cooling the devices,reducing the additional volume the PSM-HB auxiliary circuits require.

Based on the power stage designed in Section III.2 the chargeintegration circuit designed uses a 1:22 current sense transformer,loaded with R_(s)=40Ω. The op-amp integrator uses R_(f)=1 kΩ and C_(q)=1nF, resulting in a gain of approximately 0.7 V/A equivalent. Noadditional switch node capacitance was added to the main switchingdevices, such that the C_(A) and C_(N) are equal to the outputcapacitance of the MOSFET devices used. The charge references in (102)are experimentally derived and stored in a lookup table of values.Experimental derivation of the charge reference look up table was donedue to the highly non-linear nature of the output capacitance of aMOSFET device operated at variable voltage levels.

L_(aux)=80 μH was selected using available analytical models for theturn off currents of the DAB converter designed and (96), and thenreduced slightly to give a small safety margin. Auxiliary switchingdevices use a dead time 10% larger than main switching devices, and wereselected for lower output capacitance. Main switches used IRFP21N60Ldevices with an output capacitance of approximately 90 pF at 130V, whileauxiliary devices (STW20N95K) had an output capacitance of approximately40 pF at 130V.

In one embodiment, the first and second main switches Q₁, Q₂ form afirst switching leg of a full bridge switching network of the converter10 and the converter 10 includes a third main switch Q₃ connected to thepositive connection of a second switching leg and a fourth main switchQ₄ connected to negative connection of the second switching leg. Thefirst and second switching legs form a full bridge switching network.The embodiment also includes a third auxiliary switch Q₃′ connected tothe positive connection of the second switching leg, a fourth auxiliaryswitch Q₄′ connected to a negative connection of the second switchingleg, and a second auxiliary inductor L_(aux2) connected to a secondauxiliary midpoint V_(N2)′ between the third and fourth auxiliaryswitches Q₃′, Q₄′ and a second main switch midpoint V_(N2) between thethird and fourth main switches Q₃, Q₄, where the third main switch Q₃includes a third capacitance C_(N3) and the fourth main switch Q₄includes a fourth capacitance C_(N4). In the embodiment, the switchregulation module 2302 regulates switching of the third and fourthauxiliary switches Q₃′, Q₄′ to control current in the second auxiliaryinductor L_(aux2), where the second auxiliary inductor L_(aux2) providesor removes charge from the third capacitance C_(N3) and the fourthcapacitance C_(N4) to adjust voltage across the third main switch Q₃ andthe fourth main switch Q₄ to induce zero voltage switching for the thirdand fourth main switches Q₃, Q₄.

In another embodiment, the converter 10 is a DABSRC converter 100, 101,the full bridge switching network is a first full bridge switchingnetwork on a primary side 141 of the converter 10 and the converter 10includes a second full bridge switching network on a secondary side 143of the converter 10 and each switching leg of the second full bridgeswitching network includes two auxiliary switches (i.e. Q₁′, Q₂′) and anauxiliary inductor (i.e. L_(aux)) controlled by a switch regulationmodule (i.e. 2302) to achieve zero voltage switching of switches (i.e.Q₁, Q₂) in the second full bridge switching network. In one embodiment,the assisted ZVS apparatus 2300 includes a ZVS activation module 2306that activates switching of the first and second auxiliary switches Q₁′,Q₂′ and the switch regulation module 2302 when the converter 10 is in ahard switching condition.

V.2 PSM Leg ZVS Assistance Control

PSM auxiliary leg control relies on equations (105)-(107) for design ofa feedback controller. Unlike the main power flow control loop, the PSMcontrol loop is independent of converter operating point, with only thevoltage dependence of the charge reference (102) varying in response tothe applied bridge voltage. Design of the charge reference to auxiliarycurrent controller is done using digital integral controller. Thecontroller gain K_(iZVS) selected in order to maintain a phase margin ofP_(M)≧70° and a gain margin G_(M)≧10 dB. The resulting controller uses again of K_(iZVS)=100e−3, with the closed loop control to output transferfunction plotted in FIG. 28. FIG. 28 depicts PSM-HB control to outputclosed loop transfer function. The output of this controller is limitedto a maximum phase angle of π to ensure stability.

The closed loop disturbance to auxiliary current is checked to ensurethat the bandwidth is sufficiently large. As this transfer functiondetermines the speed with which a PSM auxiliary leg operated at a fixedbridge voltage can respond to changes in tank current magnitudes, abandwidth much larger than the converters main power flow bandwidth isneeded. Referencing the gain schedule controller designed in SectionIV.2 the maximum converter bandwidth is 2.76 kHz at M=1.2 andU_(CMD)=−0.5. The closed loop bandwidth of the loop relating PSM legdisturbance to auxiliary current is found to be approximately 6 kHz,which satisfies the requirement of being sufficiently larger than thatof the main power flow.

Using the controller derived above, a charge reference table still needsto be derived. Dependent on both the bridge voltage V_(A) and the switchnode capacitance C_(N) charge reference Q_(REF),

$\begin{matrix}{{Q_{REF} \geq {2\frac{R_{s}C_{N}}{{nR}_{f}C_{q}}V_{A}}},} & (111)\end{matrix}$may be computed analytically or experimentally. When a large switch nodecapacitance is added external to switching device output capacitances,analytically computing (111) becomes the desired option, as only thedirect dependence on node voltage V_(A) need be considered as all otherparameters can be considered constant. For converter legs designed withno additional capacitance, such that C_(N) is equal to the nonlinearvoltage-dependent output capacitance of a single switching device,experimental derivation of (111) is preferred. As the converter designedin III.2 does not use external capacitance on any of the switch legsexperimental derivation of Q_(REF) is preferred.

Deriving the voltage dependent charge reference table for feedbackcontrol of PSM-HB ZVS assistance involves experimentally switching asingle pair of main switches in a half-bridge configuration at anarbitrary power level where hard switching is experience and sweepingthe bridge voltage from the minimum expected value to the maximumexpected value. At each voltage level, additional current is driven intothe switch node under test by increasing the auxiliary PSM-HB phasecontrol angle until ZVS is achieved. At this point the chargeintegration output is recorded. By correlating the bridge voltage withthe output value of the charge integration circuit as seen in FIG. 25 atable can be derived relating the needed charge integration value withthe voltage across the bridge. Once the table has been completed, it isused as a reference for the PSM-HB feedback loop in order to ensure ZVSwith at all operating points.

Maintaining minimum current for PSM auxiliary circuitry soft-switchingrequires maintaining a minimum phase shift in the auxiliary legs,

$\begin{matrix}{\Phi_{N} \geq \Phi_{Min} \geq {\frac{8\pi\; f_{s}C_{A}L_{aux}}{t_{dA}}.}} & (112)\end{matrix}$Due to the nonlinear voltage dependent nature of the PSM-HB switchingdevice output capacitance C_(A) an experimentally determined table isused for Φ_(Min). This table is derived in a similar manner to the tablefor Q_(REF) as it is again dependent on bridge voltage alone.

FIG. 29 is a schematic block diagram of one embodiment of a PSM-HBfeedback circuit, incorporating bridge voltage V_(A) dependent tablesfor charge reference QREF and minimum phase shift Φ_(Min). Using boththe charge reference table and the minimum angle table, a full blockdiagram of the PSM-HB feedback circuitry is seen in FIG. 29.

V.3 ZVS Assistance with Modified MCTs in Inductively Linked Converters

When multiple converters operate together with parallel input or outputactive bridges, it becomes possible to inductively link the parallelhalf bridges of one converter with another in order to remove the needto additional PSM-HB circuitry for either the primary of the secondary.This approach allows half of the main switches in each converter to softswitch by applying a phase shift between the two converters without theneed to additional hardware. As this approach can only be used to forceZVS of half the main switching elements, it must be used in conjunctionwith a separate method in order to force ZVS of the other half of themain switching elements. One such method is to use modified MCT. Whenimplemented together, soft switching of all devices can be achievedwithout the need to additional switching elements by pairing converterstogether. This section describes one way in which this approach can beimplemented.

FIG. 83 is a schematic block diagram of one embodiment of a modified MCTapparatus 8300 in accordance with one embodiment of the presentinvention. In one embodiment, the converter 10 includes the modified MCTapparatus 8300, which may be embodied in the main power flow controller215, as depicted in FIG. 83. The apparatus 8300, in one embodiment,includes an MCT region module 8302 that defines a MCT for operationbetween a maximum positive power output to a maximum negative poweroutput of a bidirectional DC to DC converter 10. The converter 10 is aDABSRC and the MCT defines a boundary between a ZVS region and a hardswitching region. The apparatus 8300 includes an offset module 8304 thatdefines an offset to the MCT, the offset in the ZVS region, and an MCTcontrol module 8306 that adjust switching of switches of the converter10 to maintain operation of the converter in the ZVS region between themaximum positive power output to a maximum negative power output along atrajectory defined by the MCT and the offset. For example, the MCTcontrol module 8306 may control the converter 10 to operate along thepath described below in relation to FIG. 33.

In one embodiment, the MCT control module 8306 includes one or morephase shift modulators 230 that control switching of the switches of theconverter 10 by controlling a plurality of angles between switching legsof the converter 10, where each switching leg includes two switchesconnected in series between positive and negative connections to theswitching leg. For example, the switches may be similar to the switches105 of FIGS. 2A-2C. In another embodiment, the MCT control module 8306adjusts an angle φ_(AB), and angle φ_(DC), and an angle φ_(AD), asdescribed above in relation to section IV.1, operation along the MCT,and below in relation to FIG. 31. For example, angle φ_(AB) includes aphase angle between a voltage at a midpoint A between switches of afirst switching leg of the converter, v_(A), and a voltage at a midpointB between the switches of a second switching leg of the converter,v_(B), the first and second switching legs comprising a full bridgeswitching network on a primary side of the converter 10. Angle φ_(DC)includes a phase angle between a voltage at a midpoint D betweenswitches of a third switching leg of the converter, v_(D), and a voltageat a midpoint C between switches of a fourth switching leg of theconverter, v_(C), where the third and fourth switching legs form a fullbridge switching network on a secondary side of the converter 10. Angleφ_(AD) includes a phase angle between the voltage v_(A) and the voltagev_(D).

FIG. 30 is a schematic block diagram of one embodiment of a DC to DCconverter with two parallel DABSRC stages. FIG. 30 is a switchingdiagram showing phase shift modulation and definition of control anglesfor each DABSRC stage. Each DABSRC stage in FIG. 30 is modulated using athree-angle phase-shift modulation in which legs A, B, C and D are phaseshifted one with respect to the other, as detailed in FIG. 31. FIG. 31depicts Phase shift modulation and definition of control angles for eachDABSRC stage. Three independent angles exist, namely φ_(AB), φ_(AD) andφ_(DC), where φ_(XY) denotes the phase lag between nodes Y and X.Furthermore, the two stages are phase-shifted one with respect to theother by an angle φ_(AA)′. Operation of the proposed technique, detailedin the next two subsections, can be summarized as follows: controlangles v_(φ)=(φ_(AB), φ_(AD), φ_(DC)) and v′_(φ)=(φ_(A′B′), φ_(A′D′),φ_(D′C′)) are generated so as to achieve the desired power flow and toensure ZVS operation of the output devices Q₅ . . . Q₈ and Q₅′ . . .Q₈′. Power sharing is ensured by driving the two stages with the samecontrol commands: φ_(AB)=φ_(A′B′), φ_(AD)=φ_(A′D′) and φ_(DC)=φ_(D′C′),while selection of the operating vector v_(φ)=v′_(φ)=(φ_(AD), φ_(AB),φ_(DC)) is related to the required amount of active and reactive powerflow through the tank. Such relationship is derived below on the basisof a detailed power flow analysis of the DABSRC stage. On the otherhand, phase-shifting between the two DABSRC stages is accomplished bythe fourth independent control angle φ_(AA′), which serves the purposeof building an inductive current through the input auxiliary branchesL_(aux) and assist ZVS operation of input devices Q₁ . . . Q₄ and Q₁′ .. . Q₄′, as detailed below.

Equation (71) can be restated as,

$\begin{matrix}{\min\limits_{v_{\varphi}}{\left( {I_{RMS}\left( v_{\varphi} \right)} \right)\text{:}\mspace{14mu}\left\{ {\begin{matrix}{{P_{OUT}\left( v_{\varphi} \right)} = P_{OUT}} \\{{- P_{OUT}^{MAX}} \leq P_{OUT} \leq {+ P_{OUT}^{MAX}}}\end{matrix}.} \right.}} & (113)\end{matrix}$which when solved for solved for every P_(OUT)ε[−P_(OUT) ^(MAX), P_(OUT)^(MAX)], yields a parameterized curve v_(φ,MCT)(P_(OUT)) in the controlspace, referred to as the MCT. Within the fundamental approximation theMCT can be expressed in closed form and analyzed in detail; theproperties of the MCT relevant to the discussion are here summarized:

Having defined the voltage conversion ratio M as

$\begin{matrix}{M \equiv {\frac{1}{n} \cdot {\frac{V_{out}}{V_{g}}.}}} & (114)\end{matrix}$the MCT is a 2D curve lying on the φ_(DC)=180° plane in the step-downcase (M<1) or on the φ_(AB)=180° plane in the step-up case (M>1).

When M<1, the MCT involves the modulation of both angles φ_(AD) andφ_(AB); similarly, when M>1 both angles φ_(AD) and φ_(DC) are modulated.

When M=1, the MCT reduces to a one-angle modulation in which angle|φ_(AD)|≦90° controls the active power flow, while φ_(AB)=φ_(DC)=180°.Such situation corresponds to the conventional one-angle modulationconsidered.

The MCT yields, by definition, the combination of angles which resultsin the minimum flow of reactive power Q. This means that departing fromthe MCT by a controlled amount allows to control the sign and magnitudeof the reactive power flowing through the tank, and hence the reactivecomponent of the tank current.

FIG. 32 depicts one example of normalized active power contours on theφ_(DC)=180° plane, minimum current trajectory for M=0.5 andcorresponding separation between capacitive and inductive reactive powerregions. FIG. 33 depicts one example of normalized active power contourson the φ_(DC)=180° plane; the minimum current trajectory and aparticular ZVS trajectory are shown for M=0.5, together with twocorresponding operating points A_(MCT). In one embodiment, the offsetmodule 8304 defines the offset between the MCT and the ZVS trajectory inFIG. 33.

As an example, consider FIG. 32, in which the normalized active powercontours U_(OUT)=P_(OUT)/P_(OUT) ^(MAX) are illustrated on theφ_(DC)=180° plane. On the same plot, the MCT is illustrated for the caseexample M=0.5. The MCT encompasses the entire active power range[−P_(OUT) ^(MAX), +P_(OUT) ^(MAX)], connecting the maximum forward power(“MFP”) to the maximum reverse power (“MRP”) points. The MCT furtherconsists of two symmetrical branches dividing the φ_(DC)=180° plane intwo sub-regions R_(C) and R_(I). The fundamental property of these tworegions is the sign of the reactive power Q_(DC) exchanged by the tankwith the output bridge at port DC: inside the MCT, in region R_(C), onehas Q_(DC)<0 and the output bridge processes capacitive current, henceoperating in deep hard-switching mode. Inside R_(I), on the other hand,Q_(DC)>0 and switching of devices Q₅ . . . Q₈ occurs at inductivecurrents where soft turn-on can be realized. The curved branches of theMCT correspond to Q_(DC)=0. In other words, they define the boundarybetween capacitive and inductive behavior of the tank with respect tothe output bridge. On top of such branches the tank current is in phasewith the fundamental component of the reflected voltage v_(DC)/ngenerated by the output bridge on the tank.

The flat portions of the MCT extending inside region R_(I) correspond toheavy load operating points for which the minimum current operationoccurs at Q_(DC)>0. The power level at which they depart from theφ_(AB)=180° line represents the minimum power level at which deep hardswitching of the output devices can be avoided using a one-anglemodulation strategy.

It is worth observing, with this regard, that the conventional one-anglemodulation trajectory, in which φ_(AB)=φ_(DC)=180° and angle−90°≦φ_(AD)≦90° is employed to modulate the power flow, necessarilyenters the capacitive region R_(C) at light load for non-unityconversion ratios. In one embodiment, the offset includes a fixed offsetfrom the MCT in the ZVS region. In another embodiment, the offsetincludes a variable offset from the MCT in the ZVS region. For example,the offset may decrease as output power P_(OUT) increases. In anotherexample, the offset follows a trajectory similar to the ZVS trajectoryshown in FIG. 33.

FIG. 34 are tank phasor diagrams for Q_(DC)=0 (a) and on a generic ZVStrajectory (b). The MCT represents a particular one among the soughttrajectories, and precisely the one for which Q_(DC) is minimized inabsolute value. Given an arbitrary point A_(MCT) on the MCT at aspecific power level P_(OUT), the amount of inductive current throughthe tank can be increased by staying on the φ_(DC)=180° plane whilemoving the control vector inside region R_(I) along a constant P_(OUT)contour. Such action, exemplified in FIG. 33, intentionally builds up aninductive component I_(ZVS) in the tank current, orthogonal to voltagev_(DC)/n, which enables soft turn-on of the output devices. The newoperating point A_(ZVS) lies on a trajectory v_(φ,ZVS)(P_(OUT), I_(ZVS))now different from the MCT, in which the active power delivered isP_(OUT), while the reactive power has been purposely adjusted forzero-voltage switching. FIG. 34(a) and FIG. 34(b) further clarify theeffect by illustrating the tank phasor diagrams on A_(MCT) and onA_(ZVS) respectively.

Referring, for simplicity, to the M<1 case only, and with the followingdefinitions:

$\begin{matrix}{{I_{{ZVS},{FP}} \equiv {\frac{4}{n\;\pi} \cdot \frac{V_{IN}}{Z_{0}} \cdot H_{0} \cdot M}}{\alpha \equiv \frac{I_{ZVS}}{I_{{ZVS},{FP}}}}{{M^{\prime} \equiv {M - {\alpha \cdot M}}},}} & (115)\end{matrix}$and A_(ZVS) having the same active power but different amounts ofreactive power can be achieved.

Closed-form expressions for v_(φ,ZVS)(P_(OUT), I_(ZVS)) can be derivedunder the fundamental approximation already invoked previously,resulting in

$\begin{matrix}{V_{\varphi,{ZVS}}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = {{\pi \pm \pi} \mp {2\;{\arcsin\left( \sqrt{M^{\prime 2} + U_{OUT}^{2}} \right)}}}} \\{\varphi_{DC} = \pi} \\{\varphi_{AD} = {\frac{\varphi_{AB}}{2} + {\arctan\left( \frac{U_{OUT}}{M^{\prime}} \right)} - {{{sgn}\left( M^{\prime} \right)} \cdot \frac{\pi}{2}}}}\end{matrix},} \right.} & (116)\end{matrix}$when |U_(OUT)|≦(1−M′²)^(1/2), and

$\begin{matrix}{V_{\varphi,{ZVS}}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = {\varphi_{DC} = \pi}} \\{\varphi_{AD} = \left\{ \begin{matrix}{{\arcsin\left( U_{OUT} \right)},} & {{{when}\mspace{14mu}\alpha} < 1} \\{{\pi - {\arcsin\left( U_{OUT} \right)}},} & {{{when}\mspace{14mu} 1} < \alpha < {1 + \frac{1}{M}}}\end{matrix} \right.}\end{matrix},} \right.} & (117)\end{matrix}$when |U_(OUT)|>(1−M′²)^(1/2). Similar expressions can be derived for thestep-up case.

Expressions (116) correspond to the curved branches of the trajectory,with the ± sign referring to the upper or lower branch respectively.These branches are characterized by the fact that the ZVS currentsi_(D↓) and i_(C↓) of the output devices, defined as the instantaneouscurrent outsourced by node D (or C) at the turn-off instant of thehigh-side device Q₇ (or Q₅), are equal to I_(ZVS). On the other hand(117) correspond to the flat portions of the trajectory. Over theseoperating points one has i_(D↓)=i_(C↓)>I_(ZVS) because a nonzero minimuminductive current is already present in the tank, as previouslydiscussed in the context of the MCT. Quantity I_(ZVS,FP) defined in(115), represents the ZVS current at full power, and also the maximumZVS current that can be achieved or exceeded over the entire activepower range. Levels above I_(ZVS,FP) and up to (1+1/M)·I_(ZVS,FP) arepossible, but over limited power intervals and at the expense of muchlarger tank RMS currents.

Trajectories (116) and (117), parameterized in terms of the normalizedactive power U_(OUT)=P_(OUT)/P_(OUT) ^(MAX) and of the normalized ZVScurrent on the output side α=I_(ZVS)/I_(ZVS,FP), induce the (P_(OUT),Q)-to-v_(φ) mapping anticipated at the beginning of this section. It canbe proven that (116) and (117) reduces to the expression of the MCT forI_(ZVS)=0, i.e. v_(φ,ZVS)(P_(OUT), I_(ZVS)=0)=v_(φ,MCT)(P_(OUT)) forevery P_(OUT). As I_(ZVS) increases from 0 to the full-power value,trajectories of the type v_(φ,ZVS) expand deeper and deeper into theinductive power region R_(I), connecting the MRP to the MFP points by“circumventing” the capacitive power region R_(C).

While the trajectory control approach described in the previous sectionallows to exploit the degrees of freedom provided by the multi-anglemodulation to achieve full ZVS of the output devices, it exposes inputdevices Q₁ . . . Q₄ and Q₁′ . . . Q₄′ to hard switching over certainpower levels. FIG. 35 depicts normalized input turn-off currents for legB vs. normalized active power level along three different ZVStrajectories, M=0.5. The effect is exemplified for M=0.5 in FIG. 35, inwhich the theoretical turn-off current of leg B (Q₃/Q₄), indicated withi_(B↓) and normalized to the full-power amplitude of the tank current,is reported versus the normalized active power level when a standaloneDABSRC stage is operated along three different ZVS trajectories, eachcorresponding to a different level of output ZVS current α. Existence ofa i_(B↓)<0 interval implies hard-switching of devices Q₃ and Q₄ for thecorresponding power levels. Behavior of leg A, not reported here, issymmetrical with respect to the zero power point and exhibits ahard-switching interval in the reverse power range.

FIG. 84 is a schematic block diagram of another modified ZVS apparatus8400 according to one embodiment of the present invention. The apparatus8400 includes a includes an MCT region module 8302, an offset module8304, and an MCT control module 8306, which may be substantially similarto those described above in relation to the apparatus 8300 of FIG. 83.The apparatus 8400 may also include, in various embodiments, a constantcurrent module 8402, a voltage regulation module 8404, a positive powerregulation module 8406, a negative power regulation module 8408, andswitch regulation module 8410.

In one embodiment, the MCT control module 8306 includes a feed forwardcontrol loop. For example, the feed forward control loop may be asdepicted in FIG. 15 and described above. The feed forward control loopmay be part of the main power flow controller 215 and may control thephase shift modulators 230 driving the switches 105 of the resonantpower converter 100. In another embodiment, the apparatus 8400 includesa constant current module 8402 that limits output current I_(OUT) to apositive output current setpoint I_(SET) in a range between a minimumoutput voltage V_(OUT) and output power P_(OUT) of the converter 10reaching a positive power setpoint P_(SET), where the constant currentmodule 8402 includes a current feedback control loop that limits outputcurrent to below the positive output current setpoint I_(SET). Inanother embodiment, the apparatus 8400 includes a voltage regulationmodule 8404, a positive power regulation module 8406, and a negativepower regulation module 8408 which may be similar to those describedabove in section IV.3 regarding the multi-mode control apparatus 7900 ofFIG. 79. In another embodiment, the constant current feedback loopincludes compensation implemented using a gain scheduled feedbackcontroller as described above in section IV.2 Gain Scheduling FeedbackControl. The gain scheduled feedback controller may include one or moreoutput control signals that vary over a plurality of control regions andthe gain scheduled feedback controller may implement a differentcompensation equation for each control region.

In one embodiment the converter includes a second DABSRC stage asdepicted in FIG. 30. In the embodiment, the converter 10 includes twoDABSRC stages connected in parallel, where the midpoint A, A′, B, B′ onthe first and second switching legs of the two DABSRC stages are eachconnected with a link. The link includes a linking inductor L_(aux)connected in series with a linking capacitor C_(aux). The MCT controlmodule 8306 further controls a phase angle φ_(AA′) which a phase shiftbetween the voltage at the midpoint A between switches of a firstswitching leg of a first DABSRC stage, v_(A), and the voltage at themidpoint A′ between switches of a first switching leg of a second DABSRCstage, v_(A′), The MCT control module 8306 controls current in the linksbetween the two DABSRC stages to be an inductive current, where theinductive current causes one or more of the switching legs of the fullbridge switching networks on the primary sides of the two DABSRC stagesto be in a ZVS region. Operation and control of the linked DABSRC stagesis described below.

FIG. 36 depicts input ZVS operation via phase-shift between the twoDABSRC stages: main waveforms. Soft-switching on the input side cannonetheless be addressed by allowing two DABSRC stages to mutuallyassist each other via an inductive coupling between the input bridges—asillustrated in FIG. 30—combined with a controlled phase-shift φ_(AA′)between the two DABSRC stages. The effect of φ_(AA′) is that of buildingup a circulating inductive current through the auxiliary branchesL_(aux), proportional to the phase-shift itself, as sketched in FIG. 36for the coupling between nodes A and A′. The extra inductive currentI_(aux) available at each input device turn-off instant is

$\begin{matrix}{{I_{aux} = \frac{V_{g} \cdot \varphi_{{AA}^{\prime}}}{2 \cdot \omega_{s} \cdot L_{aux}}},{0 \leq \varphi_{{AA}^{\prime}} \leq {\pi.}}} & (118)\end{matrix}$

Note that auxiliary capacitors C_(aux) have the only function ofpreventing any DC current from flowing through the auxiliary branches.

Observe that phase shifting the two DABSRC stages does not impact thetrajectory control approach for output ZVS operation described above, asit relies on an additional degree of freedom, i.e. φ_(AA′), which isindependent of the control vector v_(φ)=v′_(φ). Furthermore, at heavyload, where no auxiliary current is normally needed, the proposedtechnique would null I_(aux) by saturating at φ_(AA′)=0, thereforepreserving the heavy load efficiency of the DABSRC stages.

In view of the behavior illustrated in FIG. 35, it is of interest toevaluate how much negative turn-off current needs to be counteracted atnodes A and B as a function of the ZVS level requested on the outputside. FIG. 37 illustrates the worst-case auxiliary currentI_(aux,max)—normalized to the full-power tank current amplitude—thatneeds to be injected at input nodes A/B in order to guaranteemin(i_(A↓), i_(B↓))≧0. The plot is given as function of the normalizedoutput ZVS command α and for M=0.25, 0.5, 0.75 and 1. Observe that,although I_(aux,max) is zero for sufficiently high output ZVS levels, itmust be remembered that such levels correspond to large tank RMScurrents, and that therefore such operating points may nonethelessexhibit low efficiencies due to large conduction losses. For smalleroutput ZVS levels, FIG. 37 provides a starting point for the design ofthe required inductance L_(aux).

Since based on passive coupling, the described approach has theadvantage of not requiring additional switching devices for ZVSassistance. It also allows the DC/DC unit of FIG. 30 to remain acompletely self-contained power module, prone to be paralleled/stackedwith other similar modules for more complex and scalable DC powerdistribution systems. In another embodiment, the apparatus 8400 includesauxiliary switches and an auxiliary inductor for assisted ZVS along witha switch regulation module 8410 for assisted ZVS as described inrelation to the assisted ZVS apparatus 2300 of FIG. 23 and as describedin section V.1. The assisted ZVS apparatus 2300 may be used forswitching legs not in ZVS using one of the techniques described above,such as described in relation to FIG. 33 or controlling angle φ_(AA).

The foregoing ZVS technique provides two degrees of freedom, namelyI_(ZVS) and φ_(AA′), which respectively allow a controller toindependently adjust the turn-off current at the output and input sideof the DABSRC stages. Although the work in this section focuses on thetheory and open-loop validation of the discussed ZVS technique, it isimportant to point out that both I_(ZVS) and φ_(AA′) can be adjusted bytwo independent feedback loops so as to maintain the input and outputturn-off currents at the desired set points. To this end, note thatsensing the tank current would give such ZVS assistance control loopsall the required information: as for the output turn-off current, it isthe reflected version of the tank current sampled at the turn-offinstant of any of the output devices; as for the input turn-off current,it is the sum of the tank current and of the auxiliary current, whichcan be considered known from φ_(AA′) and L_(aux) via (118).Implementation of the trajectory control equations (116) and (117) in acomputationally affordable form represents another design challengecurrently under investigation.

VI FPGA Controller Implementation

An FPGA based controller for the DABSRC has been designed based on thecontrol analysis from previous sections. Implemented on a Virtex-5 FPGAdevice and coded in Verilog Hardware Design Language, the controllerimplements a number of simplifications in order to allow the design tobe implemented in a reasonable amount of space. The FPGA used has a 100MHz system clock which is increased to 200 MHz using a clock doublingPLL and includes block RAM for the implementation of the needed lookuptables. The converter switching frequency is set by stepping down the100 MHz system clock to 97.7 kHz, and allows for 10 bit resolution inall phase shift angles. The 10 ns timing resolution possible when usinga 100 MHz system clock with 10 bit phase angle resolution means that amaximum error of 0.1% is introduced into phase control angles by thephase shift modulator. All sensing in done with 12 bits of precision andinternal computations on sensed variables are performed with 12 bitresolution. The lower two bits of 12 bit internal signals are onlyremoved by the phase shift modulator during the last step of gate drivesignal generation. The 200 MHz clock is used to access block RAM and toclock multipliers and dividers and all other logic blocks except forthose involved in the final phase shift modulator for gate drive signalgeneration.

VI.1 MCT Modulator

In order to operate the DABSRC along the MCTs derived in Section IV.1the converter output command must be translated into the correct threeangle control vector. Two approaches are possible, the first usinglookup tables and the second involving online computation of controlangels by directly implementing the equations in (74) and (75) for thestandard MCT or in (116) and (117) for the modified MCT. Only thestandard MCT calculation will be dealt with here, although only smallextensions are needed in order to implement the modified MCTcalculations.

Using lookup tables to determine MCT control angles requires a twodimensional table using both converter output command as well asconverter conversion ratio as indexes. Assuming that the converterconversion ratio is quantized as a 12 bit number K_(M) and that theconverter output command is a 12 bit number K_(UCMD) which describes thefull range of power outputs, a table for each control angle may beassembled with indexes of N_(M)≦K_(M) and N_(UCMD)≦K_(UCMD) forconversion ratio and output command respectively. Assuming N_(φ) bitsare used to represent control angles, the total table size Q_(MCT) canbe calculated asQ _(MCT)=3(2^((N) ^(M) ^(+N) ^(UCMD) ^(+N) ^(φ) ⁾).  (119)

In order to keep the total storage size below 1 Mb for reasonablestorage on an FPGA without external memory, a combined bit widthN=N_(M)+N_(UCMD)+N_(φ) of less than 18 bits is required. If only a fewconversion ratios are needed, then this approach becomes acceptable,although in general the errors introduced with this method areunacceptable if storage size is kept within reasonable limits. For thesereasons, a direct computation of the MCTs based on (74) and (75) ispreferable.

Because of the complexity of (74) and (75) simplification is usefulbefore implementation on the FPGA. To increase the symmetry of the MCTs,a new variable G,

$\begin{matrix}{G = \left\{ {\begin{matrix}{M\text{:}} & {V_{OUT} \leq V_{IN}} \\{\frac{1}{M}\text{:}} & {V_{OUT} > V_{IN}}\end{matrix},{\in \left\lbrack {0,1} \right\rbrack},} \right.} & (120)\end{matrix}$

is introduced. This simplification reduced the three MCT trajectories ofinterest to

$\begin{matrix}{\gamma_{1 +}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = {{2\pi} - {2\;{\arcsin\left( \sqrt{G^{2} + \left( U_{OUT} \right)^{2}} \right)}}}} \\{\varphi_{DC} = \pi} \\{\varphi_{AD} = {\frac{\varphi_{AB}}{2} + {\arctan\left( \frac{U_{OUT}}{G} \right)} - \frac{\pi}{2}}}\end{matrix},{{{when}{U_{OUT}}} \leq {\sqrt{1 - G^{2}}\mspace{14mu}{and}\mspace{14mu} M} \leq 1},} \right.} & (121) \\{\gamma_{2}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{AB} = {\varphi_{DC} = \pi}} \\{\varphi_{AD} = {\arcsin\left( U_{OUT} \right)}}\end{matrix},{{{when}\mspace{14mu}{U_{OUT}}} \geq \sqrt{1 - G^{2}}},} \right.} & (122) \\{\lambda_{1 +}\text{:}\mspace{14mu}\left\{ {\begin{matrix}{\varphi_{DC} = {{2\pi} - {2\;{\arcsin\left( \sqrt{G^{2} + \left( U_{OUT} \right)^{2}} \right)}}}} \\{\varphi_{AB} = \pi} \\{\varphi_{AD} = {\frac{- \varphi_{DC}}{2} + {\arctan\left( \frac{U_{OUT}}{G} \right)} + \frac{\pi}{2}}}\end{matrix},{{{when}{U_{OUT}}} \leq {\sqrt{1 - G^{2}}\mspace{14mu}{and}\mspace{14mu} M} > 1.}} \right.} & (123)\end{matrix}$

Comparing φ_(AB) in (121) with φ_(DC) in

(123) and φ_(DC) in (121) with φ_(AB) in

(123) shows that a further simplification can be made by definingoff-angle φ_(PS)φ_(PS)=2π−2 arcsin(√{square root over (G ²+(U _(OUT))²)})  (124)partial main angle φ_(X),

$\begin{matrix}{\varphi_{X} = {\arctan\left( \frac{U_{OUT}}{G} \right)}} & (125)\end{matrix}$temporary angle φ_(y)φ_(y)=arcsin(U _(OUT))  (126)and trajectory selection flag Q

$\begin{matrix}{Q = \left\{ {\begin{matrix}1 & {{U_{OUT}} \leq \sqrt{1 - G^{2}}} \\0 & {{U_{OUT}} > \sqrt{1 - G^{2}}}\end{matrix}.} \right.} & (127)\end{matrix}$

Combining (124) and 127) with (121)-(123) results in simplifiedequations for each of the three control angles,

$\begin{matrix}{\varphi_{AB} = \left\{ {\begin{matrix}\varphi_{PS} & {\left( {Q = 1} \right)\mspace{14mu}{and}\mspace{14mu}\left( {M \leq 1} \right)} \\\pi & {else}\end{matrix},} \right.} & (128) \\{\varphi_{DC} = \left\{ {\begin{matrix}\varphi_{PS} & {\left( {Q = 1} \right)\mspace{14mu}{and}\mspace{14mu}\left( {M > 1} \right)} \\\pi & {else}\end{matrix},} \right.} & (129) \\{\varphi_{AD} = \left\{ {\begin{matrix}\varphi_{y} & {Q = 0} \\{\varphi_{x} + {\frac{1}{2}\left( {\varphi_{PS} - \pi} \right)}} & {\left( {Q = 1} \right)\mspace{14mu}{and}\mspace{14mu}\left( {M \leq 1} \right)} \\{\varphi_{x} - {\frac{1}{2}\left( {\varphi_{PS} - \pi} \right)}} & {\left( {Q = 1} \right)\mspace{14mu}{and}\mspace{14mu}\left( {M > 1} \right)}\end{matrix}.} \right.} & (130)\end{matrix}$

Divisions and multiplications by 2 in (128)-(130) can be accomplishedusing bit shifts, while G² and U_(CMD) ² can be computed using either amultiplier or a look up table. The same lookup table may be used forboth quantities by taking the magnitude and bit shifting U_(CMD) beforereferencing the table. Using multipliers requires less space in general,and can again be accomplished with a single element for both G² andU_(CMD) ². To avoid computation of both an arctangent and an arcsine,the arctangents in (128)-(130) are computed using the identity

$\begin{matrix}{{\arctan(x)} = {\arcsin\left( \frac{x}{\sqrt{1 + x^{2}}} \right)}} & (131)\end{matrix}$which requires a squaring function, a square root function, and anarcsine function. With this substitution, only a square root and anarcsine remain to be computed. Fortunately the CORDIC algorithm allowscomputation of these two functions digitally on an FPGA. All functionsgenerated by a CORDIC are possible to generate using look up tables,multipliers, or power series implementations, although in general aCORDIC implementation will allow for higher accuracy in less space.

FIG. 38 is a computation flowchart for FPGA based MCT calculation.Equations (124)-(127) are calculated as seen in FIG. 38. To reduce thefabric space needed for implementation time multiplexing may be usedsuch that only a single block of each function type is needed. For thefastest computation time multiplexing is not used and FIG. 38 isimplemented directly. In either case a set of if statements are used togenerate the final control angles as seen in FIG. 39. FIG. 39 depictslogic statements needed to combine partial phase angles into finalcontrol angles.

In the prototype hardware built, computation of MCT angles is donewithout time multiplexing such that minimum time is taken to compute anew set of phase angles from output command and conversion ratio. Thisimplementation requires a total of five multipliers, three dividers, andsix CORDIC blocks. All computations use 12 bits, with operationsresulting in 24 bits such as multiplication truncated back to twelvebefore further computations are performed.

VI.2 Gain Scheduled Feedback Controller

In order to generate the output command on which the MCT calculationacts, a digital integral controller is used. This controller includes avariable gain block in order to implement the gain scheduling schemederived in Section IV.2.

The desire continuous time controller from Section IV.2 is transformedinto discrete time using the forward rectangular rule,

$\begin{matrix}{\frac{\mathbb{d}{x\left( {kT}_{s} \right)}}{\mathbb{d}t} \cong {\frac{{x\left( {{kT}_{s} + T_{s}} \right)} - {x\left( {kT}_{s} \right)}}{T_{s}}.}} & (132)\end{matrix}$By sampling the average output current at the switching frequencyf_(s)=1/T_(s)=100 kHz errors introduced by this method of conversion arekept to a minimum. The resulting feedback equation for error signal e(k)and control output U(k) becomesU[k+1]=T _(s) K _(i) e[k]+U[k].  (133)For a given discrete gain K_(i) ^(Disc)=T_(s)K_(i), two constantintegers K_(A) and K_(B) are selected such that

$\begin{matrix}{K_{i}^{Disc} = {\frac{K_{A}}{2^{K_{B}}}.}} & (134)\end{matrix}$

In this way, only integer multiplication and right-shifts are needed togenerate fractional gains. A MATAB script is used to select theappropriate parameters K_(A) and K_(B), which are stored in twodimensional look-up tables on the Virtex-5. Bit-widths for K_(A) andK_(B) are selected using a script to minimize the error between K_(i)^(Disc) and the ideal gain for each operating point. This is done issuch a way that the resulting discrete gain is never larger than itsequivalent ideal gain to ensure that stability margins are maintained.Each cycle, the current operating point is recalculated based on arunning average of the last eight samples for both current and voltage.Based on this average operating point, a new gain is selected for thecontroller every switching cycle using conversion ratio and outputcommand to index into the pre-computed K_(A) and K_(B) lookup tables.

FIG. 40 is a direct form I implementation of the output current feedbackcontroller. The digital integral controller used for current regulationof the DABSRC is implemented as a direct form I controller as seen inFIG. 40. A signed multiplier with two twelve bit inputs is used tomultiply the controller error signal by gain K_(a). The resulting 24 bitnumber is extended with 12 bits of zero and then shifted by K_(b) bitsin order to complete the full gain multiplication. This result is thendownsized with saturation to 24 bits before being summed with theprevious state. This summation is done by extending each input by asingle bit, and then saturating the result back down to 24 bits. Thisresult is stored as the previous state every switching clock cycle, andis threshold limited to 2016. The upper 12 bits of this result are usedas the new command variable which is sent into the MCT calculation codein order to generate new phase shift angles for the DABSRC hardware.

VI.3 PSM Leg ZVS Assistance Controller

The PSM leg ZVS controllers are implemented based on the results ofSection V.2. This design requires an integral controller and the use oftwo look up tables for storing both the minimum phase shift angle forensuring auxiliary leg soft switching as well as the voltage dependentcharge reference for ensuring main leg ZVS transitions as seen in FIG.41. FIG. 41 is a schematic block diagram of a ZVS controller implementedwith two lookup tables for Φ_(Min) and Q_(REF).

Each PSM-HB leg operates independently from the rest, requiring fourindividual integral controllers. For each main leg, measurements of thecharge delivered into the main switch node are taken twice a switchingcycle at both the main switch leg rising transition and fallingtransition. Ideally the two returned values are equal in magnitude butof opposite sign. Due to non-idealities, small variations exist and sothe minimum of the absolute value of the two measurements it taken. This12 bit value is then subtracted from the needed charge referenceprovided by a bus voltage dependent lookup table and multiplied by theintegral gain derived in Section V.2 using a 12 bit multiplier. The sameintegral controller setup seen in VI.2 is then used.

Each switching cycle a new minimum phase shift angle is determined usinga lookup table based on the measured bus voltage. This minimum phaseshift is applied to both the output of the integral controller block aswell as to the stored previous state. In addition to this variableminimum output, a maximum output corresponding to a nt degree phaseshift is applied.

The two lookup tables used for ZVS operation are stored in the samemanner using two port block RAM on the FPGA device. To minimize tablesize, the stored values are first level shifted such that the minimumvalue stored is zero. This reduces the number of bits needed for eachcharge reference or minimum angle but requires the level shift offset tobe reapplied before the values are used as seen in FIG. 41.

Using two port block RAM allows both the primary and secondary pairs ofPSM half bridges to index using the possibly different primary andsecondary bus voltages without regard for timing considerations as seenin FIG. 42. FIG. 42 includes ZVS lookup table connections for Φ_(Min)and Q_(REF). Two port LUTs allow only two tables to be used for all ZVslegs. Due to the unknowable phase shift between any two ZVS legs, thisgreatly reduces the complexity of implementing the ZVS assistance lookuptables. As the voltage for the primary ZVS legs is the same, and similarfor the secondary pair, only a single minimum phase shift table and asingle charge reference table are needed. As the relation between bridgevoltage and both minimum phase shift angle and charge reference is asmooth function, an extremely small table may be used to store each withlinear interpolation used between points.

VI.4 Multi-Mode Control

Multi-mode control of the DABSRC is implemented using power, voltage,and current references. Each of these references is represented as asigned 12 bit number scaled to be between −1 and 1. Using these setpoints, as well as the measured and averaged converter output voltageand current, the multi-mode controller generates a current referenceused as an input for the gain-scheduled feedback controller.

The integral controller designed in Section IV.3 and seen in (94) isimplemented on the FPGA controller as a direct form I cascadedcontroller by cascading two single pole controllers. Each single stageis implemented in the same way as described here and as seen in FIG. 43.FIG. 43 is a schematic block diagram of a single pole controllerimplementation for a cascaded two pole MMC controller.

The input signal to each stage is initially multiplied by a 12 bit gainb₀ resulting in a 24 bit signal. The saved previous state is stored as a22 bit number, which when multiplied by a 12 bit gain a₀ results in a 34bit signal. After zero extending the 24 bit scaled error, these twoquantities are summed and then downsized with saturation into a 22 bitresult. This result is next saturated to the magnitude of the convertercurrent reference and sent out of the stage as well as stored as thesaved previous state. This method for saturating the voltage and powerouter loop controllers results in smooth mode transitions. This removesthe requirement for complicated mode transition logic and greatlysimplifies the overall digital design. The output from these pairs ofcascaded controllers is a current reference needed for regulation ofeither power or voltage.

Error signals for power and voltage control are generated separatelyusing error generation modules. A current reference error signal is notnecessary, as saturation is used to enforce the current limit as seen inSection IV.3. Droop is added to the current reference using a 12 bitmultiplier before being used to saturate the voltage and powercontrollers.

Two separate voltage errors are derived in the multi-mode controller asseen in FIG. 44. FIG. 44 is a schematic block diagram of one embodimentof a MMC voltage controller error generation including droop resistance.The first error signal V_(sign) is taken as the simple differencebetween the measured output voltage and the voltage reference withoutdroop added. The upper bit of this result is then used to determine thesign of the result. This sign determines whether the converter isoperating in forward power or reverse power mode. The second voltageerror signal V_(error) is generated by first adding droop to the voltagereference. This droop is calculated by multiplying the converter outputcurrent by the voltage droop resistance, and then subtracting the resultfrom the voltage reference. This value is then subtracted from themeasured converter output voltage, resulting in a voltage error which isused for feedback control.

FIG. 45 is a schematic block diagram of one embodiment of a MMC powercontroller error generation. The power error signal (FIG. 45) isgenerated by first dividing the power set point by the absolute value ofthe measure converter output current, resulting in a 24 bit signal. Thissignal is then scaled through multiplication by a 12 bit gain dependentvoltage and current measurement ADC gains in order to keep unitscorrectly represented. This multiplication results in a 22 bit output,which is then downsized with saturation to a 12 bit result. Finally, theoutput voltage of the converter divided by 2 is subtracted from thisvalue to generate the final power error for feedback control.

FIG. 46 is a schematic block diagram of one embodiment of currentreference selection logic for MMC. In order to determine the activecontrol loop, the minimum of the absolute value of both the currentreference for voltage control, I_(REF) ^(V), and the current referencefor power control, I_(REF) ^(P), are taken (FIG. 46). If the voltagecontrol reference is the minimum quantity, then this reference isselected directly. If the power reference is the minimum quantity, thenthe sign bit found in Section VI.4 is used to determine power flowdirection. After correctly assigning the sign of the current referencefor power control, this quantity is selected. The selected currentreference I_(REF) is sent out of the multi-mode control module, and usedas a current reference for the gain scheduled current controller of theDABSRC.

VII Simulation Models

In order to verify the analytical results from the previous sections, anumber of simulation models of varying accuracy have been developed.Beginning with a full switching model including tank losses andcomponent non-idealities implemented in LTSpice, the models increase insimulation speed and decrease in complexity up to a system level modeluseful for analyzing a MMC DABSRC as part of a larger power system.

VII.1 Switching Level Models

Switching level models of the DABSRC are designed using a spicesimulator. These models provide the highest level of accuracy withrespect to hardware. Using simulation models provided by devicemanufacturers, the effect of different switching devices can beevaluated. Other non-idealities include transformer coupling and straycapacitance/inductance, resonant capacitor ESR and tank componentmismatch, switching component on resistance, as well as switch nodecapacitance.

A full model of the DABSRC including four ZVS assistance legs has beendeveloped. This model uses static control angles to investigate theoperation of the DABSRC at the desired operating point. Althoughextremely accurate, a switching level model of this accuracy takes alarge amount of time to run.

VII.2 Approximated Switching Level Models

To reduce the simulation time of a full switching level model,approximated switching models are designed in Simulink using the PLECSblock set for power electronics. These models remove many of thenon-idealities present in a full switching simulation and allow themodel to directly interface with the MATLAB environment.

The approximated switching level model developed uses a simplified tankdesign with a single capacitor and a single inductor. An ideal tanktransformer is used to further reduce simulation complexity. Tank lossesare approximated with a lumped resistor element, in order to maintainthe needed Q factor of the resonant tank. By using ideal switchingelements, simulation time is further reduced. Switch nodes include nocapacitance, either external or internal to switching elements. Thisreduces the order of the simulation and provides the greatest increasesin speed.

The approximated switching model includes a phase shift modulator inorder to generate phase shift control signals for the DABSRC. This modelassumes no quantization error on PWM outputs, and provides timingresolutions of the selected simulation time step for all reasonablevalues. Finally, an MCT calculation block may be included, allowing theDABSRC to be controlled along the MCT by using an output command,U_(CMD) to set phase angles.

VII.3 Small Signal Models

The small signal models of Section III.3 are easily implemented inMATLAB and allow simplified controller design. Additionally they may bedirectly compared with the approximated switching level model of SectionVII.2 in order to verify their accuracy.

All small signal models are stored in state space form in MATLAB due tothe reduced accuracy that a transfer function representation results infor high order models such as those describing the DABSRC. Allquantities are stated in terms of the input voltage and conversionratio, such that output voltage is not directly known in the simulationenvironment. This allows all quantities to be scaled by the inputvoltage, providing models which are independent of voltage, and onlydepend on conversion ratio and power level.

VII.4 System Level Models

In order to test the DABSRC as a component of a larger power system, asystem level model was developed. This model describes a variable numberof DABSRC stages connected together to form a converter module. Inaddition, the multi-mode controller (MMC) used to provided power,voltage and current limits is modeled to match FPGA implementations asclosely as possible without over complicating the simulations.

Two versions of this model have been designed and tested. The firstcontains a continuous controller model of the MMC, while the second is amixed signal model using a digital controller implementation. Bothmodels are interchangeable and configured the same way, although themixed signal version generally simulates faster. Both implementationsrepresent the DABSRC as a current source with a bandwidth determined bythe gain scheduled controller. In general this allows the DABSRC tofunction as a first order low pass filter with a pole at the desiredconverter bandwidth. ZVS assistance circuitry is ignored for this model,as the control loops involved have no effect on the overall system.

As the prototype hardware built uses a small microcontroller in order tointerface between a module of multiple DABSRC stages and a controlcomputer, the system level model includes an approximation of thisinterface. This portion of the model allows the system to be interactedwith in the same way and with the same commands as the physical hardwarewould be. Saturation and quantization caused by the microcontrollerinterface are included when needed.

In order to allow for arbitrary loads connected to the output of theDABSRC module, the output voltage is fed as an input into the convertermodel. This allows either a further simulation model or transferfunction to determine the relation between converter output current andvoltage. To test this functionality, a switched load was developed whichmodels constant power, voltage, resistance, or capacitance.

Finally, the system level model uses experimentally collected efficiencydata in order to estimate the system efficiency at any operating point.This is done using a table of efficiency measurements from a singleDABSRC prototype, and interpolating between points in order toapproximate system efficiency.

VIII Experimental Verification

Experimental verification was carried out using the converter designedin Section III.2. Two identical prototype converters were designed forverification so that converter interconnection could be studied.Analytical results in this chapter are compared with the modelsdeveloped in Section VII, while experimental results are generated withprototype converters running the controllers designed in Section V.

VIII.1 Prototype Converter

Prototype converters were designed using four layer PCBs with equallayer spacing and 2 OZ copper traces. Shielded differential pairconnections are used to connect each converter to its controller FPGA.Hand wound inductors are used for both auxiliary and tank components.The isolation transformer was designed and assembled off-sight. Eachconverter includes an oversized EMI filter on both the input and outputterminals. 10 kV isolation is achieved between both primary andsecondary sides of the converter. Additionally, 10 kV isolation betweenthe controllers and the converters is included. A bank of fans is usedto cool the converters, which are enclosed either in an acrylic or metalcase for safety and transport. Thermocouple sensors are attached to boththe primary and secondary main switching elements in order to monitordevice temperatures. For safety and converter protection, over voltageshutoff circuitry is included on both the primary and secondary voltagebusses.

VIII.2 Small Signal Models

The transfer functions from Section III.3 can be verified both insimulation and hardware. Mathematica was used for all transfer functioncalculations, while MATLAB was used to plot step and frequencyresponses. A tank Q factor of 25 was used for simulation.

Initial verification of converter transfer functions was done byexamining the step response of the tank current with respect to changesin control angle. FIG. 47 depicts an experimental step response of theDABSRC tank current compared to the model. Steady state control anglesat {φ_(AB)=180, φ_(AD)=84, φ_(DC)=180} with a positive 4 degree step inφ_(AD). FIG. 47 includes an experimental step response of the DABSRCtank current compared to the model. Steady state control angles at{φ_(AB)=180, φ_(AD)=84, φ_(DC)=180} with a positive 4 degree step inφ_(AD). FIG. 47 displays an experimentally obtained step response in thetank current with respect to φ_(AD). In addition an analytical stepresponse from the derived model is shown. The two show good matching interms of settling time, overshoot, and ripple frequency.

Additional verification was done by introducing a sinusoidal signal ofknown frequency and magnitude onto each control angle, and examining theFast Fourier Transform (“FFT”) of the tank current and the outputcurrent at a variety of frequencies. These points are then compared toplots of the expected frequency response. As the response of the DABSRCvaries with DC operating point, these experiments were carried out at avariety of steady state locations.

FIGS. 48-50 show the expected magnitude response of the tank currentwith respect to each of the three control angles. Experimentallygathered data on the frequency response of the tank current with respectto perturbations in φ_(AD) has been overlaid on the appropriate plot.FIG. 48 depicts simulated function

with Φ_(DC)=180°, and Φ_(AD)=90°. FIG. 49 depicts simulated function

with Φ_(AB)=180°, and Φ_(DC)=180°. Experimental data in circles for ±40perturbations are plotted on top of derived response at 3.125 kHz, 6.25kHz, 12.5 kHz, 25 kHz, and 50 kHz. FIG. 50 depicts simulated function

with Φ_(AB)=180°, and Φ_(AD)=90°.

Output current magnitude responses are plotted in FIGS. 51-53, with acomparison of experimentally measured data superimposed on FIG. 52. FIG.51 depicts simulated function H_(i) ₀ ^(ab) with Φ_(DC)=180°, andΦ_(AD)=90°. FIG. 52 depicts H_(i) _(o) ^(ab) with Φ_(AB)=180°, andΦ_(DC)=180°. Experimental data in circles for ±40 perturbations areplotted on top of derived response. FIG. 53 depicts simulated functionH_(i) _(o) ^(dc) with Φ_(AB)=180°, and Φ_(AD)=90°. The clear matching inthese results leads to the conclusion that the transfer functionsderived in this paper are reliable models of the DABSRC converter. Thebehavior seen in these results shows a high degree of transfer functionvariability with respect to control angle values, and thereforeconverter operating point. This insight into the changing behavior ofthe DABSRC affects the design of feedback controllers based around thistopology, and so proves quite useful.

VIII.3 Verification of the MCTs

The simulation model described in Section VII.2 set up in order tosimulate the foregoing design and investigate how closely the analysisdescribes the behavior of the DABSRC stage. The two major effectsaccounted for by the simulations and not considered by the theoreticalanalysis are the non-sinusoidal nature of the voltage and currentwaveforms, and a non-zero dead time t_(d). The model simulates theDABSRC in open-loop conditions with a programmable control vector v_(φ),allowing simulation of an arbitrary point in the control space C_(s).Case M=0.5 is exemplified in this section, obtained by settingV_(OUT)=200 V. Note that the maximum available power is in this casehalved with respect to the nominal rating, according to (32). A firstset of simulations was performed along the theoretical minimum currenttrajectories in the [−P_(OUT) ^(MAX), P_(OUT) ^(MAX)] range, sweepingthe operating point from the MRP to the MFP point; the positive branchγ₁₊ of the MCT was chosen as the minimum current path over the|P_(OUT)/P_(OUT) ^(MAX)|<(1−M²)^(1/2) power range.

FIG. 54 depicts simulated RMS tank current, M=0.5 example. In FIG. 54the simulated and theoretical RMS currents are reported as a function ofthe output power. Also reported is the simulated RMS tank current whenthe DABSRC is operated according to the more conventional one-anglephase-shift modulation (φ_(AB)=φ_(DC)=180°,φ_(AD)=arcsin(P_(o)/P_(o,max))). The approximated switching level modelof Section VII.2 was used for these results. As expected, a largecirculating current is observed at light load compared with the minimumcurrent operation. On the other hand the MCT brings the tank currentclose to the theoretical expected minimum in spite of the harmonicdistortion and non-zero dead time accounted by the simulation.Simulation tests were then carried out as a follow-up to the discussiondeveloped in Section IV.1 regarding the soft switching behavior of theDABSRC along the MCT.

FIG. 55(a) and FIG. 55(b) respectively report, for the M=0.5 case, thecurrents through input devices Q₁/Q₂ and Q₃/Q₄ sampled at their turn-offinstant, versus the output power P_(OUT). Predictions of the phasortransformer analysis based on the sinusoidal approximation are alsosuperimposed to the plots. The input bridge exhibits poor ZVS or hardturn-on switching around the origin as predicted, while the converteroperates in the ZVS region outside this interval. FIG. 56 depictssimulated turn-off currents of output devices Q₅ . . . Q₈ versus theoutput power, M=0.5 example. FIG. 56 reports the simulated turn-offcurrents of output devices Q₅ . . . Q₈. As previously discussed, theturn-off current remains close to zero, i.e. the output bridge operatesaround the soft/hard turn-on boundary, except for |P_(OUT)/P_(OUT)^(MAX)|>(1−M²)^(1/2) where ZVS occurs. Note that the fundamentalapproximation has stronger impact on the model accuracy here.

As anticipated in Section IV.1, when the one-angle modulation isadopted, the output bridge experiences severe hard-switching lossesbelow the critical power |P_(OUT)/P_(OUT) ^(MAX)|=(1−M²)^(1/2). Overall,one can observe how ZVS operation of the output bridge along theconventional one-angle trajectory would require the injection of astrong inductive current into the switching nodes D and C, e.g. throughsome auxiliary ZVS circuitry provision. On the other hand, a muchreduced auxiliary current would be required when operating the DABSRCalong the MCT. Similarly, a small amount of inductive current would berequired at the input side to achieve full ZVS operation. Overall, theMCT strongly reduces the criticalities in designing ZVS assistanceprovisions. These observations confirm the theoretical importance of theminimum current operation and open the possibility to more advancedtrajectory control approaches that, taking the MCT theory as a startingpoint, aim at improved ZVS and efficiency optimization.

A 1 kW DABSRC prototype was employed in experimental tests describedbelow, where 600 V, 13 A power MOSFETs IRFP21N60L were been employed aselectronic switches. The operating control vector v_(φ) is set from a PCvia a custom-made Graphic User Interface communicating with the FPGAdevice via a serial link. For the sake of definiteness, in what followsthe output power P_(OUT) is always intended as the power delivered tothe output source V_(OUT) and measured at the corresponding port.

The DABSRC prototype was first tested at nominal input and outputvoltages (M=1), using a 500 V DC power supply and an electronic loadprogrammed in constant voltage mode and set to 400 V. The setup wasemployed for both forward and reverse power tests by exchanging the DCsupply and the electronic load accordingly. The power command was sweptby adjusting angle φ_(AD) while maintaining φ_(AB)=φ_(DC)=180°. SinceM=1, such one-angle modulation also represents the minimum currenttrajectory. FIG. 57 displays experimental waveforms at 1.1 kW forwardpower, V_(g)=500V, V_(out)=400V, M=1; voltage scale: 250V/div; currentscale: 2 A/div; time scale: 2 s/div. FIG. 57 reports the experimentaltank current and voltages v_(AB)(t) and v_(DC)(t) for a 1.1 kW forwardpower operating point, at which the measured efficiency was 96%. Moreextensive efficiency measurements carried out at nominal voltage levelsare reported in FIG. 58 and demonstrate efficiencies above 95% for mostof the power range, with a peak of 98.3% at approximately P_(OUT)≈530 W.FIG. 58 depicts experimental efficiency at nominal voltage levelsV_(g)=500 V, V_(out)=400 V, M=1.

Next, the DABSRC prototype was tested at different control anglesspanning a region of the φ_(DC)=180° plane with the purpose ofexperimentally constructing the power and current contours. In order tomaintain a safe operation of the DABSRC stage where no large circulatingcurrents could damage the hardware, such tests were performed atV_(IN)=200 V input and V_(OUT)=80 V output, corresponding to ˜100 Wmaximum power and M=0.5. FIG. 59 depicts experimental vs. analyticalpower flow (a) and RMS tank current distribution (b), V_(g)=200V,V_(out)=80V, M=0.5. Comparison between analytically constructed plotsand experiments are illustrated in FIG. 59 for both the power flow andthe RMS tank current distribution. Due to the large number ofmeasurements required to construct these plots, the space explorationwas limited to a portion of the entire plane. Although some numericaldiscrepancies between experiment and model can be observed, thecomparison nonetheless reveals that the experimental trends of powerflow and current distribution compare well with the model predictions.Since the minimum current trajectory does not depend on the numericalvalue of the power flow or RMS current, but uniquely on the shape of thepower/current contours, the good match between experiment and modeldemonstrated in FIG. 59 confirms that the analytical MCT can be reliablyemployed to minimize the tank RMS current. As for the origin of theaforementioned numerical discrepancies between experimental andanalytical power and current, these can be mainly ascribed to i) theharmonic distortion of the tank current, not predicted by thefundamental approximation, ii) effects of non-zero dead time, and iii)efficiency of the experimental prototype as opposed to the perfect tankconsidered in the analysis.

Operation of the DABSRC stage along the MCT was then compared with thesimpler one-angle modulation. To this end, the stage was again tested at200 V input/80 V output (M=0.5) along the two different trajectories.FIG. 60 depicts experimental RMS tank current for minimum-currentcontrol and one-angle modulation, M=0.5, V_(g)=200V, V_(out)=80V. FIG.60 illustrates such comparison in terms of RMS tank current versusoutput power. As expected, a significant circulating current occurs withthe simpler one-angle modulation, especially at lower power levels, asopposed to the minimum current operation. As noted in the simulationresults, operation of the DABSRC along the analytical MCT brings thecurrent close to the theoretical minimum, confirming the accuracy of theanalysis even in the presence of the non-idealities of a practicalcircuit. Measured efficiencies along the MCT and along the one-anglemodulation trajectory are compared in FIG. 61. FIG. 61 depictsexperimental efficiency: minimum current trajectory vs. one-anglemodulation, M=0.5, V_(IN)=200 V, V_(OUT)=80 V. The higher efficiencyobserved along the MCT is due to the output bridge remaining at theboundary between hard and soft switching, resulting in reduced switchinglosses of the output devices.

FIG. 62 depicts experimental turn-off currents on leg D (a) and leg B(b): minimum current trajectory vs. one-angle modulation, M=0.5,V_(IN)=200 V, V_(OUT)=80 V. FIG. 62(a) further documents the switchingbehavior of the output bridge by comparing the measured turn-offcurrents of leg D along the two trajectories in the forward power range.The large negative turn-off current occurring along the one-angletrajectory is largely displaced once the DABSRC operates along the MCT.Switching behavior of the input bridge is reported in FIG. 62(b) interms of turn-off current of leg B. As anticipated by the analysis andthe simulations, the leg operates at reduced turn-off current along theMCT as opposed to the one-angle modulation trajectory. In spite of thereduced turn-off current, the severity of switching losses in thehard-switching operating region is much reduced compared withhard-switching condition of the output bridge along the one-anglemodulation path, which occurs at large negative turn-off currents asalready anticipated in FIG. 56

Advantages of operating the converter on the MCT become of criticalimportance at higher power levels. FIG. 63 depicts experimentalwaveforms relative to minimum current operation at V_(IN)=500 V,V_(OUT)=200 V, P_(OUT)=160 W. Input bridge (a) and output bridge (b).Voltage scale: 250 V/div (a), 100 V/div (b); current scale: 0.5 A/div;time scale: 1 μs/div. FIG. 63 reports screen captures relative to theminimum current operation of the prototype at V_(IN)=500V, V_(OUT)=200 Vand P_(OUT)≈160 W (M=0.5, P_(OUT) ^(MAX)≈620 W); although hard switchingoccurs on leg B, the small negative turn-off current significantlymitigates its severity. All the other legs have sufficient positiveturn-off current to initiate their resonant transitions. Efficiency atthis operating point was 82.7%. Notably, operation of the converter atthe same power level on the conventional one-angle trajectory wasimpossible to test due to overheating induced by hard switching of theoutput devices.

In light of the foregoing experimental tests and as anticipated inSection IV.1, operation along the MCT can serve as a starting point tominimize the effort required by auxiliary ZVS circuitry to optimizeefficiency.

VIII.4 PSM Leg Functional Verification

Soft start transients were taken with a bridge voltage of 130 V. FIG. 64depicts experimental data where V_(A)=130 V, soft start using PSM-HB ZVSassistance. The first transition of V_(N)′ (blue waveform)hard-switches. All other transitions soft-switch. V_(N) is seen inyellow, i_(aux) in purple, and i_(x) in green. In FIG. 64, both the mainswitch node voltage V_(N), as well as the auxiliary switch node voltageV_(N)′, are shown along with the auxiliary current i_(aux) and thenatural tank current i_(x). Comparing this result to FIG. 24, we can seethat the converter behaves as desired. Note that all voltage transitionsare smooth except for the first switching event when the auxiliary leghigh side device turns on. All waveforms are referenced as in FIG. 23.

FIG. 65 depicts experimental data where V_(A)=130 V, ZVS operationsusing PSM-HB assistance. V_(N)′ (blue waveform) is 31° shifted fromV_(N) (yellow). i_(aux), (purple) is regulated as low as possible, whilei_(x) (green) naturally achieves ZVS for main switching devices. Afterstartup, normal ZVS operation is seen in FIG. 65. For moderate powerflow operation of the DABSRC (1 A forward power for the prototype used),no additional ZVS current is needed. In this case, i_(aux)(t) isregulated to its minimum value, i_(AUX)=675 mA. A phase shift ofΦ_(N)=Φ_(MIN)=31° is applied to the auxiliary PSM-HB to enable ZVStransitions of auxiliary devices.

At a slightly lower power level (600 mA forward power), the PSM-HBfeedback loop begins to regulate a larger phase angle in order tomaintain ZVS of the main switching devices. FIG. 66 depicts experimentalresults where V_(A)=130V, ZVS operations using PSM-HB assistance. V_(N)′(blue waveform) is 40° shifted from V_(N) (yellow). i_(aux) (purple) isregulated to provide additional current for i_(x) (green) in order toobtain ZVS. In FIG. 66, a phase shift of Φ_(N)=40° is seen, resulting ini_(AUX)=860 mA. Smooth switch transitions are seen at every edge.Without ZVS assistance, the dual active bridge converter begins tohard-switch at this point, resulting in increased noise andinterference, as well as higher losses overall.

Further reducing the converter power level causes the PSM-HB feedbackloop to continuously modify Φ_(N) in order to maintain ZVS. FIG. 67depicts experimental results where V_(A)=130 V, ZVS operations usingPSM-HB assistance. V_(N)′ (blue waveform) is 39° shifted from V_(N)(yellow). i_(aux) (purple) is regulated to provide additional currentfor i_(x) (green) in order to obtain ZVS. In FIG. 67 zero power flowoperation is seen with Φ_(N)=39° and i_(AUX)=835 mA. The ZVS assistancecircuit provides the needed current for soft switching over the fullrange without requiring detailed knowledge of the wave shape andmagnitude of the converter current.

VII.5 Hybrid ZVS Assistance Verification

Experimental results for hybrid ZVS assistance were taken by connectingprototype converters as seen in FIG. 30. For these test, open loopcontrol was used for applying phase shifts between converters. Theoverall DC/DC unit was then tested with the proposed approach at anon-nominal operating point V_(g)=250 V, V_(out)=100 V. The operatingpoint, corresponding to M=0.5, was chosen as a good candidate to testthe DC/DC unit far from its nominal design voltage levels; furthermore,the maximum available power at M=0.5 is about 300 W, hence sufficientlylow to enable a comparison between the conventional and proposedtrajectories without physically harming the prototype due to hardswitching-induced overheating.

FIG. 68 depicts experimental waveforms for full ZVS operation with theproposed technique, P_(test)=110 W; voltage scale: 250V/div; currentscale: 2 A/div; time scale: 2 μs/div. FIG. 68 reports relevantexperimental waveforms at P_(OUT)=110 W, i.e. less than one twentieth ofthe nominal rating of the DC/DC unit and about one third of the maximumavailable power pertaining to the selected operating conditions. Thecontrol vector v_(φ)=(φ_(AD)=142°, φ_(AB)=312°, φ_(DC)=180°) waspositioned for a 1 A output turn-off current, while φ_(AA′)=170° wasadjusted for approximately 2 A input turn-off current. All sixteendevices in the DC/DC unit were found to operate in ZVS.

A more extensive bidirectional power sweep was performed along theconventional one-angle trajectory and along a ZVS trajectory. In thelatter case, angle φ_(AA′) was manually adjusted so as to ensure aturn-off current of at least 1 A on the input side, while the controlvectors v_(φ)=v′_(φ) were swept along the analytical curves of (116) and(117), evaluated at α=0.6 and corresponding to I_(ZVS)≈0.73 Atheoretical output turn-off current. FIG. 69 depicts experimentalefficiency of the DC/DC unit with the conventional one-angle modulationand with the proposed ZVS technique. Efficiency plots of the tests,compared in FIG. 69 demonstrate a marked improvement over theconventional one-angle modulation due to the extended ZVS range. Peakefficiency at M=0.5 is about 96%, and remains above 90% for the majorityof the power range along the ZVS trajectory. Along the one-angletrajectory, on the other hand, efficiency drops quickly as the converterdeparts from the heavy-load regions due to the trajectory enteringhard-switching region R_(C). Extra hardware for assisted ZVS operationwould be required in such case.

FIG. 70 depicts experimental input and output turn-off currents alongthe selected ZVS trajectory. The experimental input and output turn-offcurrents along the ZVS trajectory are reported in FIG. 70 for one of thetwo DABSRC stages. All the four legs of the stage operate with positiveturn-off currents as expected. The accuracy of the analytical trajectoryin determining the output ZVS current is comparable with what observedin simulation, and similar considerations hold. It is important tostress that a closed-loop control of the operating vector v_(φ) wouldhandle such residual error.

VIII.6 Gain Scheduled Controller

FIG. 71 depicts experimental data with M=0.5 and a constant gaincontroller is compared with a gain-scheduled controller. Response timeimprovements for output current steps are clearly shown. In FIG. 70three different operating points for a conversion ratio of M=0.5 arecompared. At each operating point, both a constant gain controller asdesigned for the worst case and a gain-scheduled controller as derivedin Section IV.2 are used to perform an output current step of +10% ofthe maximum available output current. At all three operating points, thegain-scheduling controller has a much faster response time whileremaining stable, with very little or no overshoot. These results areconsistent with previous analysis which shows P_(M)≧55° and a higherbandwidth at all points with a gain-scheduling controller. As the powerlevel increases, the response times of the gain-scheduling controllerapproach those of the constant gain controller. At maximum outputcurrent for M=0.5, only a slight performance improvement is seen.Experimental results verify that at M=1.2 both controllers provide thesame response characteristics near high power. All three of theseoperating points use multi-phase shift angle control of the DABSRCoperating on the MCT.

FIG. 72 depicts experimental data for an output current step response,M=1.0, I_(SET)=1.25 A stepped to I_(SET)=2.10 A, V_(IN)=300 V. FIG. 72shows a large output current reference step response at M=1.0, with aninput voltage of V_(IN)=300 V. At this conversion ratio, the DABSRC iscommanded from I_(SET)=0.2 I_(Max) to I_(SET)=0.9 I_(Max) with both again-scheduling controller as well as a constant gain controller. FIG.73 includes experimental data for a gain-scheduled feedback controllergain profile, M=1.0, I_(SET)=1.25 A stepped to I_(SET)=2.10 A,V_(IN)=300 V. FIG. 73 shows the gain-scheduled controller varying theintegral gain thorough the transient based on the averaged output power.During the transition, the integral gain is seen to oscillate betweenadjacent values. This behavior is due to slight changes in the sensedconversion ratio and power level seen by the controller during thetransient, and is due to noise and ripple on these signals. Althoughadding hysteresis to the integral gain changes could be used to avoidthis effect, the gain changes are small enough that these oscillationscan be safely ignored.

VIII.7 Multi-Mode Controller

In order to test both power sharing as well as mode transitions, themulti-mode controller designed in Section IV.3 was simulated and testedexperimentally using two converters with both series and parallel outputconnections. For simulation results the system level model from SectionVII.4 is used. The simulation is setup with two separate converters, onewith an output current regulation bandwidth of 2 kHz (converter A), andthe other with an output current regulation bandwidth of 1 kHz(converter B) in order to show the effects of mismatched controllers onpower sharing. Both converters operate with an output capacitance of 10μF. Voltage and power regulation outer loops are designed for bandwidthsof 400 Hz for both converters.

Simulation models are setup with two converters operating with seriesoutput connection for current regulation test. The converters are loadedwith a 10 kΩ resistor in parallel with a 100 μF load capacitance. Thesimulation begins with each converter output capacitor at 100 V and theload capacitor at 200 V. Both converters have a 2 A current limit and a750 W power limit. A 250 V output voltage limit is set on bothconverters in order to achieve a total of 500 V output. FIG. 74 depictssimulation results for normalized output variables for two series outputconnected converters. A capacitor charging transient is shown with powerbalance maintained throughout. At the beginning of the transient in FIG.74 both converters immediately current limit at 2 A. As converter A hasa higher bandwidth current regulation loop, it responds slightly fasterand thus achieves 2 A output voltage regulation slightly faster.Throughout this transition, both converters share power by maintainingvoltage balance across their output capacitances. Once each converterreaches 250 V, both converters enter voltage regulation mode withbalanced currents as expected with a series output connection. The powerbalance maintained during the transition from 200 V total output voltageto 500 V total output voltage validates the ability for the MMCtechnique to maintain power balance in voltage regulation mode withseries connected converters.

Simulation models are setup with two converters operating in paralleloutput connection for voltage regulation tests. As before, eachconverter is loaded with 10 μF of output capacitance. The converters areloaded with a 1 kΩ resistor. The simulation begins with 100 V across theoutput capacitance of the converter modules. Both converters have a 500V output voltage limit and a 750 W power limit. A 1 A output currentlimit is set for each converter in order to achieve 2 A total outputcurrent. FIG. 75 depicts simulation results for normalized outputvariables for two parallel output connected converters. A capacitorcharging transient is shown with power balance maintained throughout. Atthe beginning of the simulation in FIG. 75 both converters limit at 1 Aoutput current, with converter A limiting faster due to its higherbandwidth output current regulation controller. As the output voltageincreased towards its final limit of 500 V, both converters regulate at1 A output current while sharing power as expected. A total outputcurrent of 2 A is maintained throughout this period. When the outputvoltage reaches 500 V, both converters enter into voltage regulationmode to maintain 500 V output. The power balanced maintained whileregulating a 500 V output voltage validates the ability for the MMCtechnique to maintain power balance in voltage regulation mode withparallel connected converters.

Each of the three possible controller transitions was tested insimulation using the same models that were used to test power sharingduring voltage and current regulation. For all tests, both convertershave 10 μF output capacitors.

Current to power regulation transitions were verified using twoconverters operating with parallel output connections. Each converteroperates with a 1 A output current limit for a total of 2 A outputcurrent and a 500 V output voltage limit. Converter A is uses a powerlimit of 196 W while converter B uses a power limit of 200 W in order toallow both output powers to be seen on the same plot. In order to forcea current to power regulation transition, a variable load resistor of100Ω to 400Ω is used. FIG. 76 depicts simulation results for normalizedoutput variables for two parallel output connected converters. Aresistive load is used to force current to power regulation transitions.In FIG. 76, the two converters are seen to start in current regulationmode with a 100Ω load resistor. Each converter limits at 1 A outputcurrent with a total of 2 A output current. After 11.3 ms the loadresistance is switched to 400Ω forcing both converters into powerregulation mode. Converter B is seen to process slightly more power thanconverter A, which is consistent with the output power limits set. Oncesteady state is reached I power regulation mode after approximately 26ms, the output load resistor is switched back to 100Ω. This load changeforces both converters back into output current regulation mode at 1 A.The smooth transitions between output regulation modes and the powersharing achieved throughput both transitions verifies the ability of theMMC technique to handle output current to output power regulationtransitions and output power to output current regulation transitions.

Power to voltage regulation transitions were verified using twoconverters operating with series output connections. A load variableresistance loads the converter pair, is parallel with a 10 μF loadcapacitance. Both converters operate with a 2 A output current limit, a375 W output power limit, and a 250 V output voltage limit for a totalof 500 V output voltage. Initially, a 240Ω load resistor is used. Afterthe startup transient, both converters are seen to operate in powerregulation mode at 375 W in FIG. 77. FIG. 77 depicts simulation resultsfor normalized output variables for two series output connectedconverters. A resistive load is used to force power to voltageregulation transitions. At 11.3 m s the load resistance is increased to500Ω, forcing both converters to transition into output voltageregulation mode. Once steady state is reached in output voltageregulation mode, both converters are seen to regulate 250 V, for a totaloutput voltage of 500 V. After approximately 26 ms in this state, theload resistance is switched back to 240Ω. This transition forces bothconverters back into output power regulation mode. The smoothtransitions between output regulation modes and the power sharingachieved throughput both transitions verifies the ability of the MMCtechnique to handle output voltage to output power regulationtransitions and output power to output voltage regulation transitions.

Current to voltage regulation transitions were verified using twoconverters operating with parallel output connections. Each converteroperates with a 1 A output current limit for a total of 2 A outputcurrent, a 500 V output voltage limit, and a 750 W output power limit.In order to force a current to voltage regulation transition, a variableload resistor of 100Ω to 400Ω is used. FIG. 78 depicts normalized outputvariables for two parallel output connected converters. A resistive loadis used to force current to voltage regulation transitions. In FIG. 78,the two converters are seen to start in current regulation mode with a100Ω load resistor. Each converter limits at 1 A output current with atotal of 2 A output current. After 11.3 ms the load resistance isswitched to 400Ω forcing both converters into voltage regulation mode.Once steady state is reached in voltage regulation mode afterapproximately 26 ms, the output load resistor is switched back to 100Ω.This load change forces both converters back into output currentregulation mode at 1 A. The smooth transitions between output regulationmodes and the power sharing achieved throughput both transitionsverifies the ability of the MMC technique to handle output current tooutput voltage regulation transitions and output voltage to outputcurrent regulation transitions.

FIG. 80 is a schematic flowchart diagram illustrating one embodiment ofa method 8000 for multi-mode control. The method 8000 begins andcontrols 8002 output voltage V_(OUT) of a DC to DC converter 10 to anoutput voltage reference V_(SET) over an output current I_(OUT) rangebetween an operating condition where output power P_(OUT) of theconverter reaches a positive power reference P_(SET) and output powerP_(OUT) of the converter reaches a negative power reference −P_(SET).The converter 10 is a bidirectional converter. The method 8000 controls8004 output power P_(OUT) of the converter 10 to the positive powerreference P_(SET) over a positive constant power range between theoutput voltage V_(OUT) of the converter 10 being at the output voltagereference V_(OUT) and output current I_(OUT) of the converter being at apositive output current reference I_(SET).

The method 8000 controls 8006 output power P_(OUT) of the converter 10to the negative power reference −P_(SET) over a constant power rangebetween output voltage V_(OUT) of the converter 10 being at the outputvoltage reference V_(SET) and a maximum negative power limit of theconverter 10. The method 8000 limits 8008 output current I_(OUT) to apositive output current reference I_(SET) in a range between a minimumoutput voltage and output power P_(OUT) of the converter reaching thepositive power reference P_(SET), and the method 8000 ends.

FIG. 81 is a schematic flowchart diagram illustrating another embodimentof a method 8100 for multi-mode control. The method 8100 begins anddetermines 8102 if the output current I_(OUT) is below the positiveoutput current reference I_(SET). If the method 8100 determines 8102that the output current I_(OUT) is not less than the positive outputcurrent reference I_(SET), the method 8100 controls 8104 the outputcurrent I_(OUT) to the positive output current reference I_(SET). If themethod 8100 determines 8102 that the output current I_(OUT) is less thanthe positive output current reference I_(SET), the method 8100determines 8106 if the output power P_(OUT) has reached the positivepower reference P_(SET) and if the output current I_(OUT) is below thepositive output current reference I_(SET). If the method 8100 determines8106 that the output power P_(OUT) has reached the positive powerreference P_(SET) and that the output current I_(OUT) is below thepositive output current reference I_(SET), the method 8100 controls 8108the output power P_(OUT) to the positive power reference P_(SET).

If the method 8100 determines 8106 that the output power P_(OUT) has notreached the positive power reference P_(SET) and that the output currentI_(OUT) is below the positive output current reference I_(SET), themethod 8100 determines 8110 if output power P_(OUT) is between apositive power reference P_(SET) and a negative power reference −P_(SET)and if the output current I_(OUT) is less than an output currentreference I_(SET). If the method 8100 determines 8110 that the outputpower P_(OUT) is between a positive power reference P_(SET) and anegative power reference −P_(SET) and that the output current I_(OUT) isless than an output current reference I_(SET), the method 8100 controls8112 output voltage V_(OUT) to the output voltage reference V_(SET).

If the method 8100 determines 8110 that the output power P_(OUT) is notbetween a positive power reference P_(SET) and a negative powerreference −P_(SET) or that the output current I_(OUT) is not less thanan output current reference I_(SET), the method 8100 determines 8114 ifthe output power P_(OUT) has reached the negative power reference−P_(SET) and if the output power P_(OUT) is below a maximum negativepower limit. If the method 8100 determines 8114 that the output powerP_(OUT) has reached the negative power reference −P_(SET) and that theoutput power P_(OUT) is below a maximum negative power limit, the method8100 controls 8116 output power P_(OUT) to the negative power reference−P_(SET). The method 8100 returns and continues to monitor output powerP_(OUT), output current I_(OUT), and output voltage V_(OUT) against thesetpoints and limits described above.

FIG. 82 is a schematic flowchart diagram illustrating another embodimentof a method 8200 for assisted ZVS. The method 8200 begins optionallydetermines 8202 if a switching leg of a DC to DC converter 10 is in ahard switching mode. If the method 8200 determines that the switchingleg of the converter 10 is not in a hard switching mode, for example inZVS, the method 8200 returns and determines 8202 if the switching leg ofthe converter 10 is in a hard switching mode. If the method 8200determines that the switching leg of the converter 10 is in a hardswitching mode, the method 8200 activates 8204 switching of the firstand second auxiliary switches Q₁′, Q₂′. The method 8200 senses 8204senses current i_(aux) in the auxiliary inductor L_(aux) and senses 8204current i_(x) in the connection between elements of the converter 10 andthe main switch midpoint V_(N) and regulates 8206 switching in the firstand second auxiliary switches Q₁, Q₂ of the switching leg, and themethod 8200 ends.

The method 8200 may use the current i_(aux) sensed 8204 in the auxiliaryinductor L_(aux) and current i_(x) in the connection between theelements of the converter 10 and the main switch midpoint V_(N) and mayuse switching states of the first and second main switches Q₁, Q₂ toregulate 8206 switching in the first and second auxiliary switches Q₁′,Q₂′ to adjust current i_(aux) in the auxiliary inductor to adjustvoltage across the first and second main switches Q₁, Q₂ to achieve zerovoltage switching. In another embodiment, regulating 8206 switching ofthe first and second auxiliary switches Q₁′, Q₂′ may include controllingcurrent i_(aux) in the auxiliary inductor L_(aux) by controlling a phaseangle Φ_(N) between a voltage transition at the auxiliary midpoint andthe main switch midpoint.

FIG. 85 is a schematic flowchart diagram illustrating an embodiment of amethod 8500 for modified MCT control. The method 8500 begins by defining8502 a MCT for operation between a maximum positive power output to amaximum negative power output of the converter 10, where the converterincludes a DABSRC 100, 101. The MCT defines a boundary between a ZVSregion and a hard switching region. In one embodiment, the MCT regionmodule 8302 defines 8502 the MCT. The method 8500 includes defining 8504an offset to the MCT, where the offset is in the ZVS region, andadjusting 8506 switching of switches of the converter 10 to maintainoperation of the converter in the ZVS region between the maximumpositive power output to a maximum negative power output along atrajectory defined by the MCT and the offset, and the method 8500 ends.In one embodiment, the offset module 8304 defines 8304 the offset andthe MCT control module 8306 adjusts 8506 switching of the converter 10.

FIG. 86 is a schematic flowchart diagram illustrating another embodimentof a method 8600 for modified MCT control. The method 8600 begins bydefining 8602 a MCT for operation between a maximum positive poweroutput to a maximum negative power output of the converter 10, where theconverter includes a DABSRC 100, 101. The MCT defines a boundary betweena ZVS region and a hard switching region. The method 8600 includesdefining 8604 an offset to the MCT, where the offset is in the ZVSregion, and adjusting 8606 switching of switches of the converter 10 tomaintain operation of the converter in the ZVS region between themaximum positive power output to a maximum negative power output along atrajectory defined by the MCT and the offset.

The method 8600 adjusts 8608 current a link between linked DABSRC stagesto control ZVS in one or more switching legs. For example, the converter10 may include linked DABSRC stages as depicted in FIG. 30, which may becontrolled as described above in section V.3. The method 8600 may alsoinclude controlling 8610 auxiliary switches Q₁′, Q₂′ to control currentin an auxiliary inductor L_(aux) to control ZVS in a switching leg, asdescribed above in section V.2, and the method 8600 ends.

The present invention may be embodied in other specific forms withoutdeparting from its spirit or essential characteristics. The describedembodiments are to be considered in all respects only as illustrativeand not restrictive. The scope of the invention is, therefore, indicatedby the appended claims rather than by the foregoing description. Allchanges which come within the meaning and range of equivalency of theclaims are to be embraced within their scope.

What is claimed is:
 1. An apparatus comprising: a voltage regulationmodule that controls output voltage of a direct current (“DC”) to DCconverter to an output voltage reference over an output current rangebetween an operating condition where output power of the converterreaches a positive power reference and output power of the converterreaches a negative power reference, the converter comprising abidirectional converter; a positive power regulation module thatcontrols output power of the converter to the positive power referenceover a positive constant power range between the output voltage of theconverter being at the output voltage reference and output current ofthe converter being at a positive output current reference; a negativepower regulation module that controls output power of the converter tothe negative power reference over a constant power range between outputvoltage of the converter being at the output voltage reference and amaximum negative power limit of the converter; and a constant currentmodule that limits output current to a positive output current referencein a range between a minimum output voltage and output power of theconverter reaching the positive power reference.
 2. The apparatus ofclaim 1, wherein the constant current module comprises a currentfeedback control loop that limits output current to below the positiveoutput current reference.
 3. The apparatus of claim 2, wherein thepositive power regulation module, the negative power regulation module,and the voltage regulation module comprise feedback control loops andwherein the current feedback control loop comprises an inner feedbackcontrol loop and the feedback control loops of the positive powerregulation module, the negative power regulation module, and the voltageregulation module comprise an outer feedback loop.
 4. The apparatus ofclaim 2, wherein the constant current feedback loop further comprisescompensation implemented using a gain scheduled feedback controller, thegain scheduled feedback controller comprising one or more output controlsignals that vary over a plurality of control regions, the gainscheduled feedback controller implementing a different compensationequation for each control region.
 5. The apparatus of claim 4, whereinthe converter comprises one or more phase shift modulators controlled bythe one or more output control signals, wherein the one or more outputcontrol signals control according to a minimum current trajectory(“MCT”) control technique, the MCT substantially minimizing circulatingcurrent within the converter.
 6. The apparatus of claim 4, wherein thegain scheduled feedback controller maintains the converter in azero-voltage switching (“ZVS”) region while minimizing circulatingcurrent by following a trajectory a fixed distance from an MCT.
 7. Theapparatus of claim 1, wherein the constant current module further limitsthe output current to a negative output current reference in a rangebetween a minimum output voltage and output power of the converterreaching the negative power reference.
 8. The apparatus of claim 1,wherein the output voltage reference varies with output current suchthat the output voltage reference decreases as output current increases.9. The apparatus of claim 8, wherein the output voltage reference variesbased on the equation:V _(Set)(I _(O))=V _(Set)(0)−I _(OUT) R _(V) where: V_(Set)(I_(O)) isthe output voltage reference as a function of output current V_(Set)(0)is the output voltage reference at zero output current; R_(V) is aresistance representing a slope of the output voltage reference; andI_(OUT) is output current of the converter.
 10. The apparatus of claim1, wherein the positive output current reference varies with outputvoltage such that the positive output current reference decreases asoutput voltage increases.
 11. The apparatus of claim 10, wherein thepositive output current reference varies based on the equation:${I_{Set}\left( V_{OUT} \right)} = {{I_{Set}(0)} - \frac{V_{OUT}}{R_{I}}}$where: I_(Set)(V_(OUT)) is the positive output current reference as afunction of output voltage; I_(Set)(0) is the positive output currentreference at zero output voltage; V_(OUT) is the output voltage; andR_(I) is a resistance representing a slope of the positive outputcurrent reference.
 12. The apparatus of claim 1, wherein the convertercomprises a resonant power converter.
 13. The apparatus of claim 12,wherein the resonant power converter comprises at least one stage of adual active bridge series resonant converter (“DABSRC”).
 14. A systemcomprising: a direct current (“DC”) to DC converter, the convertercomprising a bidirectional converter; one or more phase shift modulatorscontrolling one or more phase angles within the converter; a voltageregulation module that controls output voltage of the converter to anoutput voltage reference over an output current range between anoperating condition where output power of the converter reaches apositive power reference and output power of the converter reaches anegative power reference; a positive power regulation module thatcontrols output power of the converter to the positive power referenceover a positive constant power range between the output voltage of theconverter being at the output voltage reference and output current ofthe converter being at a positive output current reference; a negativepower regulation module that controls output power of the converter tothe negative power reference over a constant power range between outputvoltage of the converter being at the output voltage reference and amaximum negative power limit of the converter; and a constant currentmodule that limits output current to a positive output current referencein a range between a minimum output voltage and output power of theconverter reaching the positive power reference.
 15. The system of claim14, wherein the constant current module comprises a current feedbackcontrol loop that limits output current to below the positive outputcurrent reference.
 16. The system of claim 15, wherein the constantcurrent feedback loop further comprises compensation implemented using again scheduled feedback controller, the gain scheduled feedbackcontroller comprising one or more output control signals that vary overa plurality of control regions, the gain scheduled feedback controllerimplementing a different compensation equation for each control region.17. The system of claim 16, wherein the one or more output controlsignals control according to a minimum current trajectory (“MCT”)control technique, the MCT substantially minimizing circulating currentwithin the converter, wherein the gain scheduled feedback controllermaintains the converter in a zero-voltage switching (“ZVS”) region whileminimizing circulating current by following a trajectory a fixeddistance from an MCT.
 18. A method comprising: controlling outputvoltage of a direct current (“DC”) to DC converter to an output voltagereference over an output current range between an operating conditionwhere output power of the converter reaches a positive power referenceand output power of the converter reaches a negative power reference,the converter comprising a bidirectional converter; controlling outputpower of the converter to the positive power reference over a positiveconstant power range between the output voltage of the converter beingat the output voltage reference and output current of the converterbeing at a positive output current reference; controlling output powerof the converter to the negative power reference over a constant powerrange between output voltage of the converter being at the outputvoltage reference and a maximum negative power limit of the converter;and limiting output current to a positive output current reference in arange between a minimum output voltage and output power of the converterreaching the positive power reference.
 19. The method of claim 18,wherein limiting output current to a positive output current referencecomprises using a current feedback control loop that limits outputcurrent to below the positive output current reference.
 20. The methodof claim 18, wherein controlling output voltage of the converter to anoutput voltage reference, controlling output power of the converter tothe positive power reference, and controlling output power of theconverter to the negative power reference comprise using one or moreouter feedback control loops to the current feedback control loop, whichcomprises an inner feedback control loop.
 21. The method of claim 18,wherein limiting output current to a positive output current referencecomprises generating one or more output control signals that vary over aplurality of control regions, wherein each control region comprises adifferent compensation equation.
 22. The method of claim 18, furthercomprising varying the output voltage reference with output current suchthat the output voltage reference decreases as output current increases,wherein the output voltage reference varies based on the equation:V _(Set)(I _(O))=V _(Set)(0)−I _(OUT) R _(V) where: V_(Set) (I_(O)) isthe output voltage reference as a function of output current V_(Set)(0)is the output voltage reference at zero output current; R_(V) is aresistance representing a slope of the output voltage reference; andI_(OUT) is output current of the converter.
 23. The method of claim 18,further comprising varying the positive output current reference withoutput voltage such that the positive output current reference decreasesas output voltage increases, wherein the positive output currentreference varies based on the equation:${I_{Set}\left( V_{OUT} \right)} = {{I_{Set}(0)} - \frac{V_{OUT}}{R_{I}}}$where: I_(Set) (V_(OUT)) is the positive output current reference as afunction of output voltage; I_(Set)(0) is the positive output currentreference at zero output voltage; V_(OUT) is the output voltage; andR_(I) is a resistance representing a slope of the positive outputcurrent reference.